Algorithm of Modified Single-slope A/D Converter with Improved Conversion Time for CMOS Image Sensor System

Title & Authors
Algorithm of Modified Single-slope A/D Converter with Improved Conversion Time for CMOS Image Sensor System
Lee, Sang-Hoon; Kim, Jin-Tae; Shin, Jang-Kyoo; Choi, Pyung;

Abstract
This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $\small{2^n}$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $\small{0.35-{\mu}m}$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.
Keywords
Single-slope A/D converter;Conversion time;Pipeline A/D converter;A/D converter;CMOS image sensor;
Language
English
Cited by
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