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Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory
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 Title & Authors
Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory
Seo, Juwan; Choi, Min;
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This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.
Disturbance Minimization;Erase Verify;NAND Flash Memory;Stress Reduction;
 Cited by
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