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Design of a 512b Multi-Time Programmable Memory IPs for PMICs
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 Title & Authors
Design of a 512b Multi-Time Programmable Memory IPs for PMICs
Jang, Ji-Hye; Ha, Pan-Bong; Kim, Young-Hee;
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 Abstract
In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (
 Keywords
MTP Cell;PMIC;Multi-Time Programmable;Negative Voltage;Single Poly EEPROM;
 Language
Korean
 Cited by
 References
1.
Analysis of the Status Quo in the Power Semiconductor, Electronics Information Center, July 2010.

2.
H. S. Chun, "Market Outlook and Domestic and Global Development Trend for Power Semiconductor," IITA Weekly Technology Trends, June 2009.

3.
H. Park, S. H. Lee, M. H. Park, P. B. Ha, Y. H. Kim, "Design of Small-Area Dual-Port eFuse OTP Memory IP for Power ICs," JKIIECT, vol. 8, no. 4, pp.310-318, Aug. 2015.

4.
Y. N. Yu, L. Y. Jin, K. I. Kim, M. S. Kim, Y. B. Park, M. H. Park, P. B. Ha, Y. H. Kim, "Design of 256 bit Single-Poly MTP Memory Based on BCD Process," J. Cent. South Univ. Technol., vol. 19, no. 12, pp. 3460-3467, Dec. 2012. crossref(new window)

5.
J. H. Jang, H. Park, S. H. Lee, P. B. Ha, Y. H. Kim, " Design of MTP IP for PMIC'" ISSN 2005-0496, pp.143-146, June, 2015.

6.
F. Torricelli, L. Milani. L. Colalongo, A. Richelli, Kovacs-Vajna, Z.M., "Half-MOS Based Single-Poly EEPROM Cell With Program and Erase Bit Granularity," IEEE Electron Device Letters, vol. 34, no. 12, Dec. 2013.

7.
Roizin, Yakov, E. Pikhay, V. Dayan, A. Heiman, "High Density MTP Logic NVM for Power Management Applications", IEEE International Memory Workshop 2009, pp. 1-2, 2009.

8.
J. C. Lee J. C. Kim, S. H. Kim, "A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications," Journal of the Korean Physical Society, Vol.41, No.6, pp.846-850, Dec. 2002.

9.
J. Raszka, V. Tiwari, A. Mittal, M. Han, A. Shubat, "Embedded Flash Memory for Security Applications in a $0.13{\mu}m$ CMOS Logic Process," IEEE ISSCC Tech. Dig., pp. 46-47, Feb. 2004.

10.
Y. H. Kim, "Single Poly EEPROM Memory," KR. patent 10-1357847, Feb. 5, 2014.