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Design of a 512b Multi-Time Programmable Memory IPs for PMICs
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 Title & Authors
Design of a 512b Multi-Time Programmable Memory IPs for PMICs
Jang, Ji-Hye; Ha, Pan-Bong; Kim, Young-Hee;
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In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (
MTP Cell;PMIC;Multi-Time Programmable;Negative Voltage;Single Poly EEPROM;
 Cited by
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