JOURNAL BROWSE
Search
Advanced SearchSearch Tips
A Design of a Tile Based Rasterizer Using Memory Hierarchy Structure
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
  • Journal title : Journal of IKEEE
  • Volume 19, Issue 4,  2015, pp.590-595
  • Publisher : Institude of Korean Electrical and Electronics Engineers
  • DOI : 10.7471/ikeee.2015.19.4.590
 Title & Authors
A Design of a Tile Based Rasterizer Using Memory Hierarchy Structure
Kim, Do Hyun; Kwak, Jae Chang;
  PDF(new window)
 Abstract
This paper proposes a design of efficient hierarchy structure in the tile based rasterizer. The proposed hierarchy structure avoids unnecessary calls of low level tile at which a calculation is not required. A low level tile is classified into three categories based on its maximum, minimum position, and inside outside test. The necessity of calculations on the corresponding low level tile can be determined by its classification. The overall amount of computations for graphic processing can be reduced by not calling for the low level tile with no calculation. The proposed hierarchy structure can reduce an execution time of graphic processing. It shows higher efficiency with the more vertex density of formulating 3D model.
 Keywords
Rasterizer;tile-based randering;Hierarchy structure;Inside outside test;Coner;
 Language
Korean
 Cited by
 References
1.
Dong-young Yeo, "A Design of a 3D Graphics pipeline based on Multi-core Processor", The Graduate School of Seokyeong University, 2011.2

2.
Dool-Bong Jeon, "A Design of Rasterizer including clipping and culling function for a Mobile Graphics", The Graduate School of Seokyeong University, 2008.2

3.
Jang-seo Ku, "Design of a Rasterizer based on Parallel Processing Interpolation Algorithm for a Mobile GPU", The Graduate School of Seokyeong University, 2013.2

4.
Jeong-Ho Woo, "Mobile 3D Graphics SoC From Algorithm to Chip", WILEY, 2010

5.
Ramchan Woo, "Design and Implementation of Low-Power 3D Graphics SoC for Mobile Multimedia Applications", KAIST, 2004.6.

6.
W.F.P.W. Burgers "Tile-Based Rendering", Master's thesis. Technische Universiteit Eindhoven, Eindhoven, 2005.1

7.
Woo-Young Kim, "A Design of a Shader based on the Variable-Length Instruction for a Mobile GP-GPU", The Graduate School of Seokyeong University, 2010.2

8.
Xilinx, "VC707 User Guide", http://www.xilinx.com