Publisher : Institude of Korean Electrical and Electronics Engineers
DOI : 10.7471/ikeee.2015.19.4.590
Title & Authors
A Design of a Tile Based Rasterizer Using Memory Hierarchy Structure Kim, Do Hyun; Kwak, Jae Chang;
This paper proposes a design of efficient hierarchy structure in the tile based rasterizer. The proposed hierarchy structure avoids unnecessary calls of low level tile at which a calculation is not required. A low level tile is classified into three categories based on its maximum, minimum position, and inside outside test. The necessity of calculations on the corresponding low level tile can be determined by its classification. The overall amount of computations for graphic processing can be reduced by not calling for the low level tile with no calculation. The proposed hierarchy structure can reduce an execution time of graphic processing. It shows higher efficiency with the more vertex density of formulating 3D model.