Design of Unified Inverse Transformer for HEVC and VP9

• Journal title : Journal of IKEEE
• Volume 19, Issue 4,  2015, pp.596-602
• Publisher : Institude of Korean Electrical and Electronics Engineers
• DOI : 10.7471/ikeee.2015.19.4.596
Title & Authors
Design of Unified Inverse Transformer for HEVC and VP9
Jung, Seulkee; Lee, Seongsoo;

Abstract
In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $\small{4{\times}4{\sim}32{\times}32}$ HEVC IDCT, $\small{4{\times}4}$ HEVC IDST, $\small{4{\times}4{\sim}32{\times}32}$ VP9 IDCT, $\small{4{\times}4{\sim}16{\times}16}$ VP9 IADST and $\small{4{\times}4}$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $\small{4{\times}4}$ IDST and VP9 $\small{4{\times}4}$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.
Keywords
Language
Korean
Cited by
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