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Design of a SIMT architecture GP-GPU Using Tile based on Graphic Pipeline Structure
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  • Journal title : Journal of IKEEE
  • Volume 20, Issue 1,  2016, pp.75-81
  • Publisher : Institude of Korean Electrical and Electronics Engineers
  • DOI : 10.7471/ikeee.2016.20.1.075
 Title & Authors
Design of a SIMT architecture GP-GPU Using Tile based on Graphic Pipeline Structure
Kim, Do-Hyun; Kim, Chi-Yong;
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This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to `RAMP` and previous studies.
SIMT;tile-based graphic pipeline;Hierarchy structure;Inside outside test;Rasterization;
 Cited by
The parallelization of binarization using a GP-GPU, The International Journal of Advanced Culture Technology, 2016, 4, 4, 57  crossref(new windwow)
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