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Design of a SIMT architecture GP-GPU Using Tile based on Graphic Pipeline Structure
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  • Journal title : Journal of IKEEE
  • Volume 20, Issue 1,  2016, pp.75-81
  • Publisher : Institude of Korean Electrical and Electronics Engineers
  • DOI : 10.7471/ikeee.2016.20.1.075
 Title & Authors
Design of a SIMT architecture GP-GPU Using Tile based on Graphic Pipeline Structure
Kim, Do-Hyun; Kim, Chi-Yong;
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This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.
SIMT;tile-based graphic pipeline;Hierarchy structure;Inside outside test;Rasterization;
 Cited by
Laszlo, E., "Methods to utilize SIMT and SIMD instruction level parallelism in tridiagonal solvers," Cellular Nanoscale Networks and their Applications (CNNA), 2014 14th International Workshop on, 2014.07

Pinto, C., "GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms, Cluster," Cloud and Grid Computing (CCGrid), 2011 11th IEEE/ACM International Symposium on, pp.53-62, 2011.05

W.F.P.W. Burgers "Tile-Based Rendering," Master's thesis. Technische Universiteit Eindhoven, Eindhoven, 2005.1

Ramchan Woo, "Design and Implementation of Low-Power 3D Graphics SoC for Mobile Multimedia Applications," KAIST, 2004.6.

Jang-seo Ku, "Design of a Rasterizer based on Parallel Processing Interpolation Algorithm for a Mobile GPU," The Graduate School of Seokyeong University, 2013.2

Kim, Sung Su, "Table-based thread reconvergence mechanism on SIMT processor," The Graduate School of Yonsei University, 2011.12

Jeong-Ho Woo, "Mobile 3D Graphics SoC From Algorithm to Chip," WILEY, 2010

Woo-Young Kim, "A Design of a Shader based on the Variable-Length Instruction for a Mobile GP-GPU," The Graduate School of Seokyeong University, 2010.2