JOURNAL BROWSE
Search
Advanced SearchSearch Tips
A Development of Fusion Processor Architecture for Efficient Main Memory Access in CPU-GPU Environment
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
A Development of Fusion Processor Architecture for Efficient Main Memory Access in CPU-GPU Environment
Park, Hyun-Moon; Kwon, Jin-San; Hwang, Tae-Ho; Kim, Dong-Sun;
  PDF(new window)
 Abstract
The HSA resolves an old problem with existing CPU and GPU architectures by allowing both units to directly access each other`s memory pools via unified virtual memory. In a physically realized system, however, frequent data exchanges between CPU and GPU for a virtual memory block result bottlenecks and coherence request overheads. In this paper, we propose Fusion Processor Architecture for efficient access of main memory from both CPU and GPU. It consists of Job Manager, Re-mapper, and Pre-fetcher to control, organize, and distribute work loads and working areas for GPU cores. These components help on reducing memory exchanges between the two processors and improving overall efficiency by eliminating faulty page table requests. To verify proposed algorithm architectures, we develop an emulator based on QEMU, and compare several architectures such as CUDA(Compute Unified Device Architecture), OpenMP, OpenCL. As a result, Proposed fusion processor architectures show 198% faster than others by removing unnecessary memory copies and cache-miss overheads.
 Keywords
CPU-GPU;GPGPU;Uniform Memory Access;HSA;Fusion architecture;
 Language
Korean
 Cited by
 References
1.
J. Power, A. Basu, J. Gu, S. Puthoor, B. M. Beckmann, M. Dill, and D. Aood, "Heterogeneous system coherence for integrated CPU-GPU systems," Proceedings of the 46th Annual IEEE/ACM Int. Symposium on Microarchitecture. ACM, California, USA, Dec. 2013. pp. 457-467.

2.
C. Balkesen, J. Teubner, G. Alonso, and M. T. Ozsu, "Main-memory hash joins on multicore CPUs: Tuning to the underlying hardware," Data Engineering (ICDE), 2013 IEEE 29th Int. Conf. on. IEEE, Brisbane, Australia, April 2013. pp. 362-373.

3.
B. Pichai, L. Hsu, and A. Bhattacharjee. "Architectural support for address translation on gpus: Designing memory management units for cpu/gpus with unified address spaces," ACM Special Interest Group on Programming Languages(SIGPLAN) Notices, vol. 49 no.4, 2014, pp 743-758.

4.
G. Kim, M. Lee, J. Jeong, and J. Kim, "Multi-GPU system design with memory networks," Proceedings of the 47th Annual IEEE/ACM Int. Symposium on Microarchitecture. IEEE Computer Society, Cambridge, United Kingdom, Dec. 2014. pp. 484-495

5.
J. Jeffers and J. Reinders, High Performance Parallelism Pearls Volume Two: Multicore and Many-core Programming Approaches, Waltham: Morgan Kaufmann, 2015.

6.
B. Hechtman, A. Blake, and J. Daniel, "Evaluating cache coherent shared virtual memory for heterogeneous multicore chips," Performance Analysis of Systems and Software (ISPASS), 2013 IEEE Int. Symposium on. IEEE, Texas, USA, April. 2013. pp. 118-119.

7.
S. Potluri, H. Wang, D. Bureddy, A. Singh, C. Rosales, and D. Panda, "Optimizing MPI communication on multi-GPU systems using CUDA inter-process communication," Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International. IEEE, Shanghai, China, May 2012. pp. 1848-1857.

8.
S. Lin, Y. Liao, and Y. Hsu, "A Reliable and Secure GPU-Assisted File System," Algorithms and Architectures for Parallel Processing. Springer Int. Publishing, vol. 8630, 2014, pp. 71-84.

9.
I. Singh, A. Shriraman, W. Fung, M. O'Connor, and T. Aamodt, "Cache coherence for GPU architectures," on High Performance Computer Architecture (HPCA), 19th International Symposium on, 2013, pp. 578-590.

10.
S. Kim and Y. Choi, "Analysis of Human Activity Using Motion Vector and GPU," J. of the Korea Institute of Electronic Communication Sciences, vol. 9, no. 10, 2014, pp. 1095-1102. crossref(new window)

11.
J. Park, "Comparison Speed of Pedestrian Detection with Parallel Processing Graphic Processor and General Purpose Processor," J. of the Korea Institute of Electronic Communication Sciences, vol. 10, no. 2, 2015, pp. 239-246. crossref(new window)

12.
S. Lee and W. Jeong, "Design of the Entropy Processor using the Memory Stream Allocation for the Image Processing," J. of the Korea Institute of Electronic Communication Sciences, vol. 7, no. 5, 2012, pp. 1017-1026.