Advanced SearchSearch Tips
Study on the Relationship between Concentration of JGB and Current Density in TSV Copper filling
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Study on the Relationship between Concentration of JGB and Current Density in TSV Copper filling
Jang, Se-Hyun; Choi, Kwang-Seong; Lee, Jae-Ho;
  PDF(new window)
The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with diameter were obtained.
via filling;copper electroplating;leveler;JGB;current density;
 Cited by
J. Sun, K. Kondo, T. Okamura, S. J. Oh, M. Tomisaka, H. Yonemura and M. Hoshino, "High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking", J. Electrochem. Soc., 150(6), G55 (2003).

M. Hirano, K. Nishikawa, I. Toyoda, S. Aoyama, S. Sugitani and K. Yamasaki, "Three-dimensional Interconnect Technology for Ultra-compact MMICs", Solid-State Electron., 41(10), 1451 (1997). crossref(new window)

S. Sheng, A. Chandrakasan and R. W. Brodersen, "A Portable Multimedia Terminal", IEEE Commun. Mag., 30(12), 64 (1992).

T. Yoshinaga and M. Nomura, "Trends in R&D in TSV Technology for 3D LSI Packaging", Science & Technology Trends, Quarterly Rev., 37, 26 (2010).

N. Tanaka and Y. Yoshimira, "Ultra-Thin 3D-Stacked SiP Formed Using Room-Temperature Bonding between Stacked Chips", Proc. 54th Electronic Components and Technology Conf., 788 (2005).

S. Miura and H. Honma, "Advanced Copper Electroplating for Application of Electronics", Surf. Coat. Technol., 91, 169 (2003).

L. Hofmann, R. Ecke, S. E. Schulz and T. Gessner, "Investigations Regarding Through Silicon Via Filling for 3D Integration by Periodic Pulse Reverse Plating with and without Additives", Microelectron. Eng., 88(5), 705 (2011). crossref(new window)

D. Josell, B. Baker, C. Witt, D. Wheeler and T. P. Moffat, "Via Filling by Electrodeposition", J. Electrochem. Soc., 149(12), C637 (2002). crossref(new window)

T. P. Moffat, D. Wheeler, S. K. Kim and D. Josell, "Curvature Enhanced Adsorbate Coverage Mechanism for Bottom-Up- Superfilling and Bump Control in Damascene Processing", Electrochim. Acta, 53, 145 (2007). crossref(new window)

S. K. Kim, D. Josell and T. P. Moffat, "Electrodeposition of Cu in the PEI-PEG-Cl-SPS Additive System", J. Electrochem. Soc., 153(9), C616 (2006). crossref(new window)

S. J. Lee, Y. J. Jang, J. H. Lee and J. P. Jung, "Cu-Filling Behavior in TSV with Positions in Wafer Level", J. Micro-electron. Packag. Soc., 21(4), 91 (2014).

T. P. Moffat, D. Wheeler, C. Witt and D. Josell, "Superconformal Electrodeposition Using Derivitized Substrates", Electrochem. Solid-State Lett., 5(12), C110 (2002). crossref(new window)

W. P. Dow and M. Y. Yen, "Microvia Filling over Self-Assembly Disulfide Molecule on Au and Cu Seed Layers", Electrochem. Solid-State Lett., 8(11), C161 (2005). crossref(new window)

W. P. Dow, C. C. Li, M. W. Lin, G. W. Su and C. C. Huang, "Copper Fill of Microvia Using a Thiol-Modified Cu Seed Layer and Various Levelers", J. Electrochem. Soc., 156(8), D314 (2009). crossref(new window)

M. W. Jung, K. T. Kim, Y. S. Koo and J. H. Lee, "The Effects of Levelers on Electrodeposition of Copper in TSV Filling", J. Microelectron. Packag. Soc., 19(2), 55 (2012).