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Design and Implementation of Image-Pyramid
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 Title & Authors
Design and Implementation of Image-Pyramid
Lee, Bongkyu;
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 Abstract
This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.
 Keywords
Image Pyramid;Multi-resolution;Visual System;Gaussian Pyramid;
 Language
English
 Cited by
 References
1.
B. Blair and C. Murphy, Difference of Gaussian Scale-Space Pyramids for SIFT Feature Detection, Complex Digital Systems Design, Final report, 2007.

2.
P.J. Burt, “Fast Filter Transforms for Image Processing,” Journal of Computer Graphics and Image Processing, Vol. 16, No. 1, pp. 20-51, 1981. crossref(new window)

3.
J. Yang, X. Chen, and W. Kunz, “A PDA-based Face Recognition System,” Proceedings of Winter Application Computer Vision, pp. 457-460, 2002.

4.
T. G. Link, N. Vijaykrishnan, M. J. Irwin, and W. Wolf, “Embedded Hardware Face Detection,” Proceedings of the 17th International Conferenceon VLSI Design, pp. 1221-1232, 2004.

5.
O. Sims and J. Irvine, “An FPGA Implementation of Pattern-selective Pyramidal Image Fusion,” Proceedings of 2006 International Conference of Field Programmable Logic and Application, pp. 345-349, 2006.

6.
N. Petterson and L. Petterson, “Online Stereo Calibration using FPGAs,” IEEE Proceedings of Intelligent Vehicles Symposium, pp. 780-784, 2005.

7.
A. Darabiha, W.J. MacLean, and J. Rose, “Reconfigurable Hardware Implementation of a Phase-correlation Stereo Algorithm,” Machine Vision and Applications, Vol. 17, No. 2, pp. 116-132, 2006. crossref(new window)

8.
P.J. Burt and E.H. Adelson, “The Laplacian Pyramid as a Compact Image Code,” IEEE Transactions on Communications, Vol. 31, No. 6, pp. 532-540, 1983. crossref(new window)

9.
Zhen-jun Du and Min Li, “SoC Verification Based on WGL,” Journal of Korea Multimedia society, Vol. 9, No. 12, pp. 1607-1616, 2006

10.
P.G.D. Valle, D. Atienza, G. Paci, and F. Poletti, “Application of FPGA Emulation to SoC Floorplan and Packaging Exploration,” Proceeding of XXII Conference on Design of Circuits and Integrated System, pp. 236-240, 2003.

11.
M. Brogatti, F. Lertora, B. Foret, and L. Cali, “A Reconfigurable System Featuring Dynamically Extensible Embedded Microprocessor, FPGA, and Customizable I/O,” IEEE Journal of Solid- State Circuits, Vol. 38, No. 6, pp. 521-529, 2003. crossref(new window)

12.
R. McCready, “Real-Time Face Detection on a Configurable Hardware System”, Proceedings of International Symposium on FPGA, pp. 23-26, 2000.