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Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)
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 Title & Authors
Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)
Kim, Kee-Won; Lee, Won-Jin; Kim, HyunSung;
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Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient multiplier in GF() using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O() area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.
Exponentiation;Modular multiplication;Finite field;Public-key cryptosystem;
 Cited by
W.W. Peterson, E.J. Weldon Jr., "Error-Correcting Codes," MIT Press, Cambridge, 1972.

R.E. Blahut, "Theory and Practice of Error Control Codes," Addison-Wesley, 1983.

W. Diffie, M.E. Hellman, "New directions in cryptography," IEEE Trans. Infom. Theory, Vol. 22, No. 6, pp.644-654. 1976. crossref(new window)

B. Schneier, "Applied Cryptography", John Wiley & Sons Inc., 1996.

서화정, 김호원, "속성기반 재 암호화를 이용한 스마트카드 인증권한 분배스킴," 대한임베디드공학회 논문지, Vol. 5, No. 3, pp.168-174, 2010.

S.W. Wei, "A systolic power-sum circuit for $GF(2^m)$," IEEE Trans. Comput., Vol. 43, No. 2, pp.226-229, 1994. crossref(new window)

C.L. Wang, J.H. Guo, "New systolic arrays for $AB^2+C$, inversion, and division in $GF(2^m)$," IEEE Trans. Comput., Vol. 49, No. 10, pp.1120-1125, 2000. crossref(new window)

C.Y. Lee, E.H. Lu, L.F. Sun, "Low-complexity bit-parallel systolic architecture for computing $AB^2+C$ in a class of finite field $GF(2^m)$," IEEE Trans. Circuits Systems II, Vol. 48, No. 5, pp.519-523, 2001. crossref(new window)

K.M. Ku, K.J. Ha, K.Y. Yoo, "Design of new $AB^2$ multiplier over $GF(2^m)$ using cellular automata," IEE Proceedings on Circuits Devices Systems, Vol. 151, No. 2, pp.88-92, 2004. crossref(new window)

W.H. Lee, K.J. Lee, K.Y. Yoo, "New digit-serial systolic arrays for power-sum and division operation in $GF(2^m)$," Lecture Notes in Computer Science, Vol. 3045, pp.638-647, 2004. crossref(new window)

C.Y. Lee, A.W. Chiou, J.M. Lin, "Low-complexity bit-parallel systolic architectures for computing $A(x)B^2(x)$ over $GF(2^m)$," IEE Proceedings on Circuits Devices Systems, Vol. 153, No. 4, pp.399-406, 2006. crossref(new window)

C.Y. Lee, "Concurrent Error Detection in Systolic Array $AB^2$ Multiplier Using Linear Codes," Proceedings on International Conference on Computational Aspects of Social Networks (CASoN), pp.111-115, 2010.

S.M. Kang, Y. Leblebici, "CMOS Digital Integrated Circuits Analysis and Design," McGraw-Hill, 1999.