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Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)
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 Title & Authors
Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)
Kim, Kee-Won; Lee, Won-Jin; Kim, HyunSung;
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 Abstract
Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient multiplier in GF() using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O() area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.
 Keywords
Exponentiation;Modular multiplication;Finite field;Public-key cryptosystem;
 Language
Korean
 Cited by
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