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Efficient Integrated Design of AES Crypto Engine Based on Unified Data-Path Architecture
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 Title & Authors
Efficient Integrated Design of AES Crypto Engine Based on Unified Data-Path Architecture
Jeong, Chan-Bok; Moon, Yong-Ho;
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 Abstract
An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.
 Keywords
AES;Cryptography;Security;Verilog;Xilinx Synthesis;
 Language
Korean
 Cited by
 References
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