JOURNAL BROWSE
Search
Advanced SearchSearch Tips
An Implementation of SoC FPGA-based Real-time Object Recognition and Tracking System
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
An Implementation of SoC FPGA-based Real-time Object Recognition and Tracking System
Kim, Dong-Jin; Ju, Yeon-Jeong; Park, Young-Seak;
  PDF(new window)
 Abstract
Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.
 Keywords
SoC FPGA;HPS;Nios II processor;Real-Time;Object recognition;Tracking;
 Language
Korean
 Cited by
 References
1.
Todd Koelling, User-customized ARM-based SoC FPGA for Next-Generation Embedded Systems, Embedded News, Dec., 2011 (in Korean).

2.
E.J. Hwang, User-Customized ARM-based SoC, Embedded News, July, 2012 (in Korean).

3.
SangHaifeng, XuChao, "Moving Object Detection Based on Background Subtraction of Block Updates," IEEE International Conference on Intelligent Networks and Intelligent Systems, pp.51-54, 2013.

4.
K.I. Kim, "Binary Connected-component Labeling with Block-based Labels and a Pixel-based Scan Mask", Journal of The Institute of Electronics Engineers of Korea, Vol, 50, No. 5, pp.1307-1314, 2013 (in Korean).

5.
Cyclone V Hard Processor System Technical Reference Manual, pp.1-3323, 2014.

6.
Altera Corp., Avalon Interface Specifications, pp.1-58, 2015.

7.
Altera Corp., Quartus II Handbook, pp.1-1767, 2014

8.
Altera Corp., Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices, pp.1-30, 2011.