Advanced SearchSearch Tips
An Efficient Variable Rearrangement Technique for STT-RAM Based Hybrid Caches
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
An Efficient Variable Rearrangement Technique for STT-RAM Based Hybrid Caches
Youn, Jonghee M.; Cho, Doosan;
  PDF(new window)
The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.
Cache;Memory subsystem;Variable;Performance;Energy;
 Cited by
X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, Y. Chen, "Circuit and microarchitecture evaluation of 3D stacking magnetic ram (mram) as a universal memory replacement," Proceedings of 45th ACM/IEEE Design Automation Conference, pp. 554-559, 2008.

X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, Y. Xie, "Hybrid cache architecture with disparate memory technologies," Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 34-45, 2009.

P. Mangalagiri, K. Sarpatwari, A. Yanamandra, V. Narayanan, Y. Xie, M. J. Irwin, O. A. Karim, "A low-power phase change memory based hybrid cache architecture," Proceedings of the 18th ACM Great Lakes Symposium on VLSI, pp. 395-398, 2008 (in Korean).

Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, Y. Xie, "Energy and endurance-aware design of phase change memory caches," Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe, pp. 136-141, 2010.

X. Wu, J. Li, L. Zhang, E. Speight, Y. Xie, "Power and performance of read-write aware hybrid caches with non-volatile memories," Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe, pp. 737-742, 2009.

B.S. Jung, J.H. Lee, "Effective Algorithm for the Low-Power Set-Associative Cache Memory," IEMEK J. Embed. Sys. Appl., Vol. 9, No. 4, 2014 (in Korean).

Q. Li, M. Zhao, Y. He, "Compiler assisted preferred caching for embedded systems with STTMRAM based hybrid cache," Proceedings of the 13th ACM SIGPLAN/ SIGBED International Conference on Languates, Compilers, Tools and Theory for Embedded Systems, pp. 109-118, 2012.

T. Janjusic, K. Kavi, "Gleipnir: a memory tracing and profiling tool," ACM SIGARCH Computer Architecture News, Vol. 41, No. 4, pp. 8-12, 2012.

C. Lattner, V. Adve, "LLVM: A compilation framework for lifelong program analysis & transformation," Proceedings of International Symposium on Code Generation and Optimization, pp. 75-86, 2004.

M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, R.B. Brown, "Mibench: A free, commercially representative embedded benchmark suite," Proceedings of IEEE International Workshop on Workload Characterization, pp. 3-14, 2001.

C.K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V.J. Reddi, K. Hazelwood, "Pin: building customized program analysis tools with dynamic instrumentation," Proceedings of the ACM SIGPLAN conference on Programming language design and implementation, pp. 190-200, 2005.

J. Li, C. Xue, Y. Xu, "Stt-ram based energy-efficiency hybrid cache for cmps," Proceedings of IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, pp. 31-36, 2011.

N. Muralimanohar, R. Balasubramonian, N. Jouppi, "Optimizing nuca organizations and wiring alternatives for large caches with cacti 6.0," Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 3-14, 2007.