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A Performance Study of Asymmetric Embedded Multi-Core Processors
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 Title & Authors
A Performance Study of Asymmetric Embedded Multi-Core Processors
Lee, Jongbok;
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 Abstract
Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.
 Keywords
asymmetric multi-core embedded processor;dual-core;quad-core;octa-core;hexadeca-core;
 Language
Korean
 Cited by
 References
1.
J. Balfour et. al, "An Energy-Efficient Processor Architecture for Embedded Systems," IEEE Computer Architectures, Vol. 7, No. 1, Jun. 2008.

2.
J. Lee, "A Performance Study of Embedded Multicore Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 13, no. 1, pp. 163-169, Feb. 2013.

3.
R. Kumar et al, "Single-ISA heterogeneous Multicore Architectures for Heterogeneous for Multithreaded Workload Performance," Annual International Symposium on Computer Architecture, Mar. 2004.

4.
Hourd, Jon, et al. "Exploring Practical Benefits of Asymmetric Multicore Processors," Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, Apr. 2009.

5.
T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002

6.
G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, "Multiscalar Processors," Proceedings of the 22nd annual international symposium on Computer architecture, pp. 414-425, May 1995.

7.
T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May. 1992.

8.
J. Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 12, no. 3, pp. 9-13, Jun. 2012.

9.
M. R. Guthaus, J. S. Ringenberg, D. Ernest, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A free, commercial representative embedded benchmark suite," Workload Characterization, pp. 3-14, Dec. 2001.

10.
T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002. crossref(new window)