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Design of a On-chip LDO regulator with enhanced transient response characteristics by parallel error amplifiers
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 Title & Authors
Design of a On-chip LDO regulator with enhanced transient response characteristics by parallel error amplifiers
Son, Hyun-Sik; Lee, Min-Ji; Kim, Nam Tae; Song, Han-Jung;
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This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix CMOS parameters. Chip layout size is . Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.
Capacitor-less;LDO regulator;On-chip;Parallel error amplifier;PMIC;
 Cited by
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