Design of a On-chip LDO regulator with enhanced transient response characteristics by parallel error amplifiers

Title & Authors
Design of a On-chip LDO regulator with enhanced transient response characteristics by parallel error amplifiers
Son, Hyun-Sik; Lee, Min-Ji; Kim, Nam Tae; Song, Han-Jung;

Abstract
This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $\small{0.18{\mu}m}$ CMOS parameters. Chip layout size is $\small{500{\mu}m{\times}150{\mu}m}$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.
Keywords
Capacitor-less;LDO regulator;On-chip;Parallel error amplifier;PMIC;
Language
Korean
Cited by
References
1.
Ho, Edward NY, and Philip KT Mok. "A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application.", IEEE transaction on circuits and system, Vol. 57, No. 2, pp. 80-84, 2010. DOI: http://dx.doi.org/10.1109/TCSII.2009.2038630

2.
Lee, Hoi, Philip KT Mok, and Ka Nang Leung. "Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators.", IEEE transaction on circuits and systems, Vol. 52, No. 9, pp. 563-567, 2005. DOI: http://dx.doi.org/10.1109/TCSII.2005.850781

3.
Rincon-Mora, Gabriel, and Phillip E. Allen. "Optimized frequency-shaping circuit topologies for LDOs.", IEEE Transactions on circuits and systems, Vol. 45, No. 6, pp. 703-708, 1998. DOI: http://dx.doi.org/10.1109/82.686689

4.
Rincon-Mora, Gabriel. Analog IC Design with Low-Dropout Regulators (LDOs). McGraw-Hill, Inc., 2009.

5.
Baker, R. Jacob. CMOS: circuit design, layout, and simulation. Vol. 18. John Wiley & Sons, 2011.

6.
Guo, Jianping, and Ka Nang Leung. "A 6-W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology.", IEEE Journal of solid-state circuits, Vol. 45, No. 9, pp. 1896-1905, 2010. DOI: http://dx.doi.org/10.1109/JSSC.2010.2053859

7.
Gavriel A, Rincon-mora, pilip E. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE Journal of solid-stage circuits, Vol. 33, No. 1, pp. 36-44, 1998. DOI: http://dx.doi.org/10.1109/4.654935

8.
Bo-Min Kwon, Han-Jung Song "Design of the LDO Regulator with 2-stage wide-band OTA for High Speed PMIC, The Korea Academia-Industrial Cooperation Society, Vol. 11, No 4, pp. 1222-1228, 2010. DOI: http://dx.doi.org/10.5762/KAIS.2010.11.4.1222