Advanced SearchSearch Tips
A 12-bit Hybrid Digital Pulse Width Modulator
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
A 12-bit Hybrid Digital Pulse Width Modulator
Lu, Jing; Lee, Ho Joon; Kim, Yong-Bin; Kim, Kyung Ki;
  PDF(new window)
In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.
DC/DC converter;PT calibration;Digital PWM;ADC;
 Cited by
B. J. Patella, A. Prodic, A. Zirger and D. Maksimovic, "High frequency digital PWM controller IC for DC/DC converters," IEEE Trans. on Power Electronic, Vol. 18, Issue 1, Part 2, pp. 438-446, 2003. crossref(new window)

A. V. Peterchev, S. R. Sanders, "Quantization resolution and limit cycling in digitally controlled PWM converters," IEEE Trans. on Power Electronic, Vol. 18. Issue 1, Part 2, pp. 208-215, 2007.

H. C. Foong, Y. Zheng, Y. K. Tan and M. T. Tan, "Fast-transient integrated digital DC-DC converter with predictive and feedforward control," IEEE Trans. on Circuits and Systems 1: Regular Papers. Vol. 59, Issue 7, pp. 1567-1576, 2012. crossref(new window)

A. Syed, E. Ahmed, D. Maksimovic and E. Alarcon, "Digital pulse width modulator architectures," IEEE 35th Annual Power Electronics Specialists Conference, Vol. 6, pp. 4689-4695, 2004.

A. V. Peterchev, J. Xiao and S. R. Sanders, "Architecture and IC implementation of a digital VRM controller," IEEE Transactions on Power Electronics. Vol. 18, Issue 1, Part 2, pp. 356-364, 2003. crossref(new window)

N. R. Mahapatra, S. V. Garimella and A. Taree, "An empirical and analytical comparison of delay elements and a new delay element design," IEEE Computer Society Workshop on VLSI, pp. 81-86, 2000.

B. Razavi, "Design of analog integrated circuits," McGraw-Hill, pp. 390-392, 2000.

K. K. Kim and Y. B. Kim, "A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems," IEEE Trans. on Very Large Scale Integration (VLSI) systems, Vol. 17, Issue 4, pp. 517-528, 2009. crossref(new window)

B. V. Hieu, S. Choi, J. Seon and et. al., "A new approach to the thermometer-to-binary encoder of flash ADCs-bubble error detection circuit," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2011.