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Asynchronous Circuit Design Combined with Power Switch Structure
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 Title & Authors
Asynchronous Circuit Design Combined with Power Switch Structure
Kim, Kyung Ki;
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This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.
Asynchronous circuit;Power Switch Structure;Low Power Design;
 Cited by
J. Pangjun & S.S. Sapatnekar, "Low-power Clock Distribution Using Multiple Voltages and Reduced Swings," IEEE Trans. on VLSI Systems, Vol 10, pp. 309-318, 2002. crossref(new window)

Huajun Chi, Sangman Kim, and Jusung Park, "Mixed Dual-rail Data Encoding Method Proposal and Verification for Low Power Asynchronous System Design," Journal of IEEK, Vol 51, No.7, pp. 66-102, 2014.

Myeong-Hoon Oh, "Design of QDI Model Based Encoder/Decoder Circuits for Low Delay-Power Product Data Transfers in GALS Systems," Journal of IEEK (SD), Vol 43, No.1, pp. 27-37, 2006.

P. A. Beerel, R. O. Ozdag and M. Ferretti, "A Designer's Guide to Asynchronous VLSI", Cambridge University Press, 2010.

Scott C. Smith, Jia Di, "Designing Asynchronous Circuits using NULL Convention Logic (NCL)," Morgan & Claypool Publishers, 2009.

F. A. Parsan, W. K. Al-Assadi, S. C. Smith, "Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits," IEEE Trans. on VLSI Systems, Vol 22, Issue 1, pp.99-112, Jan. 2014. crossref(new window)

Kyung Ki Kim, "Design and Implementation of low power ALU based on NCL (Null Convention Logic)," Journal of the Korea Industrial Information System Society , Vol 18, No.5, pp. 59-65, 2013.

K. Shi and D. Howard, "Challenges in sleep transistor design and implementation in low-power designs," in Proc. IEEE Design Automation Conf., pp. 113-116, July 2006.

M. Anis, S. Areibi and M. Elmasry, "Design and optimization of multi-threshold CMOS (MTCMOS) circuits," IEEE Tran. on CAD of Integrated Circuits and Systems, Vol. 22, No. 10, pp. 1324-1242, Oct. 2003. crossref(new window)

H. W. Lee, H. J. Lee, J. K. Woo, W. Y. Shin, S. Kim, "Power-gating structure with virtual power-rail monitoring mechanism," Journal of Semiconductor Technology and Science, Vol 8 No.2, pp. 110-181, June 2008.

Kyung Ki Kim, "Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells," Journal of the Korea Industrial Information System Society , Vol 19, No.6, pp. 1-6, 2014.

Wook Hun Hong, Kyung Ki Kim, "Design of Ultra Low-Voltage NCL Circuits in Nanoscale MOSFET Technology," Journal of the Korea Industrial Information System Society , Vol 17, No.4, pp. 17-23, 2012.

F. A. Parsan and S. C. Smith, "CMOS Implementation of Static Threshold Gates with Hysteresis: A New Approach," IEEE MWSCAS, pp.394-397, Aug. 2012.