Asynchronous Circuit Design Combined with Power Switch Structure

Title & Authors
Asynchronous Circuit Design Combined with Power Switch Structure
Kim, Kyung Ki;

Abstract
This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $\small{4{\times}4}$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.
Keywords
Asynchronous circuit;Power Switch Structure;Low Power Design;
Language
Korean
Cited by
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