- Volume 15 Issue 3
Simulated annealing is an attractive, but expensive, heuristic method for approximating the solution to combinatorial optimization problems. Attempts to parallel simulated annealing, particularly on distributed memory multicomputers, are hampered by the algorithm's requirement of a globally consistent system state. In a multicomputer, maintaining the global state S involves explicit message traffic and is a critical performance bottleneck. To mitigate this bottleneck, it becomes necessary to amortize the overhead of these state updates over as many parallel state changes as possible. By using this technique, errors in the actual cost C(S) of a particular state S will be introduced into the annealing process. This paper places analytically derived bounds on this error in order to assure convergence to the correct optimal result. The resulting parallel simulated annealing algorithm dynamically changes the frequency of global updates as a function of the annealing control parameter, i.e. temperature. Implementation results on an Intel iPSC/2 are reported.
- Science v.220 Optimization by Simulated Annealing Kirkpatrick, S.;Gellatt, C.D. Jr.;Vecci, M.P.
- Simulated Annealing: Theory and Applications van Laarhoven, P.J.M.;Aarts, E.H.L.
- Chem. Physics v.21 Equation of State Calculations by Fast Computing Machines Metropolis, N.;Rosenbluth, A.;Rosenbluth, M.;Teller, A.;Teller, E.
- Mathl. Comput. Modeling v.16 no.1 Composite Stock Cutting Through Simulated Annealing Lutfiyya H.;McMillin, B.;Poshyanonda, P.;Dagli, C.
- A Taxonomy of Parallel Simulated Annealing Techniques, Computer Science Technical Report, CSD-890050 Greening, D.R.
- Proc. the International Conference on Computer Design Error Tolerance in Parallel Simulated Annealing Technique Jayaraman, R.;Darma, F.
- Proc. the International Conference on Computer-Aided Design A New Simulated Annealing Algorithm for Standard Cell Placement Grover, L.K.
- IEEE Trans. on Parallel and Distributed System v.1 no.1 Parallel Simulated Annealing Algorithm for Cell Placement on Hypercube Multiprocessors Banerjee, P.;Jones, M.H.;Sargent, J.S.
- IEEE Design and Test Parallel Simulated Annealing: Accuracy versus speed in placement Durand, M.D.
- IEEE Transactions on Computer-Aided Design A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells Casotto, A.;Romeo, F.;Sangiovanni-Vincentelli, A.
- Proc. International conference on Computer-Aided Design Fast, High Quality VLSI Placement on an MIMD Multiprocessor Rose, J.S.;Blythe, D.R.;Snelgrove, W.M.;Vranesic, Z.G.
- IEEE Design & Test of Computers Multipurpose Parallelism for VLSI CAD on the RP3 Darema, F.;Pfister, G.F.
- Proc. the International Conference on Computer-Aided Design Floorplanning by Annealing on a Hypercube Multiprocessor Jayaraman, R.;Rutenbar, R.A.
- IEEE Trans. on Computer-Aided Design v.9 no.3 Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placement Jonathan Rose;Wolfgang Klebsch;Wolf, J.
- Proc. IEEE Int. Conference on Computer Design Concepts of Scales in Simulated Annealing White, S.R.