IDDQ Test Pattern Generation in CMOS Circuits

CMOS 조합회로의 IDDQ 테스트패턴 생성

  • 김강철 (여수대학교 컴퓨터공학과) ;
  • 송근호 (경상대학교 전자공학과) ;
  • 한석붕 (경상대학교 전자공학과)
  • Published : 1999.03.01

Abstract

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

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