A study on the synchronization parameter to design ADSL chip in DMT systems

DMT시스템에서 ADSL 칩 설계를 위한 동기화 파라미터에 관한 연구

  • 조병록 (순천대학교 전자공학과) ;
  • 박솔 (순천대학교 전자공학과) ;
  • 김영민 (전남대학교 전자공학과)
  • Published : 1999.09.01

Abstract

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

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