Thermal Behavior of Flow Pattern Defect and Large Pit in Czochralski Silicon Crystals and Effects of Large Pit upon Device Yield

쵸크랄스키 Silicon 단결정의 Large Pit과 Flow Pattern defect의 열적 거동과 Large Pit의 소자 수율에의 영향

  • Song, Yeong-Min (Division of Materials Engineering, Chungnam National University) ;
  • Mun, Yeong-Hui (Division of Materials Engineering, Chungnam National University) ;
  • Kim, Jong-O (Division of Materials Engineering, Chungnam National University) ;
  • Jo, Gi-Hyeon (LG Siltron)
  • 송영민 (충남대학교 공과대학 재료공학과) ;
  • 문영희 (충남대학교 공과대학 재료공학과) ;
  • 김종오 (충남대학교 공과대학 재료공학과) ;
  • 조기현
  • Published : 2001.09.01

Abstract

The thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystal was investigated by applying high temperature annealing ($\geq$$1100^{\circ}C$) and non-agitated Secco etching. For evaluation of the effect of LP upon device performance/yield, commercial DRAM and ASIC devices were fabricated. The results indicated that high temperature annealing generates LPs whereas it decreases FPD density drastically. However, the origins of FPD and LP seemed to be quite different by not showing any correspondence to their density and the location of LP generation and FPD extinction. By not showing any difference between the performance/yield of devices whose design rule is larger than 0.35 $\mu\textrm{m}$, LP seemed not to have detrimental effects on the performance/yield.

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