Characteristics of Si Nano-Crystal Memory

  • Published : 2001.03.01

Abstract

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}V_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

References

  1. S. Tiwari, F. Rana, K. Chan, and D. Buchanan, 'Volatile and Non-volatile Memores in Silicon with Nano-crystal storage,' in IEDM Tech. Dig., pp. 521-524, 1995 https://doi.org/10.1109/IEDM.1995.499252
  2. H. I. Hanafi, S. Tiwari, and I. Khan, 'Fast and Long Retention- Time Nano-Crystal Memory,' IEEE Trans. Electron Devices, vol. 38, pp. 1553-1558, 1996 https://doi.org/10.1109/16.535349
  3. S. Tiwari, F. Rana, K. Chan , L. Shi, and H. Hanafi, 'Single charge and confinement effects in nano-crystal memories,' Appl. Phys. Lett., vol. 69, pp. 1232-1234, 1996 https://doi.org/10.1063/1.117421
  4. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki, 'A Room-Temperature Single-Electron Memory Device Using Fine-Grain Polycrystaline Silicon,' in IEDM Tech. Dig., pp. 541-544, 1993 https://doi.org/10.1109/IEDM.1993.347292
  5. W. C. Lee, and C. Hu, 'Modeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling,' in Symp. VLSI Technology Dig. Tech. Papers, pp. 198-199, 2000 https://doi.org/10.1109/VLSIT.2000.852824
  6. K. Han, W. Kim, H. Kang and H. Shin, 'Two Band Tunneling Currents in Dual-Gate CMOSFET with Ultrathin Gate Oxide,' in Proc. Int. Conf Superlattices, Microstructures, and Microdevices, pp.108-109, 2000
  7. H. Shin and J. Lee, 'Optimization of Silicon Quantum Dot Fabrication on Oxide and Nitride Films,' Journal of Electrical Engineering and Information Science, vol. 4, pp. 519-522, 1999
  8. I. Kim, S. Han, K. Han, J. Lee, and H. Shin, 'Room Temperature Single Electron Effects in a Si Nano-Crystal Memory,' IEEE Electron Device Lett., vol. 20, pp.630-631, 1999 https://doi.org/10.1109/55.806109
  9. I. Kim, S. Han, B. Choi, S. Hwang, and H. Shin, 'Room Temperature Single Electron Effect in Si Quantum Dot Memory with Oxide-Nitride Tunneling Dielectrics,' in IEDM Tech. Dig., pp. 111-114, 1998 https://doi.org/10.1109/IEDM.1998.746291
  10. I. Kim, K. Han, S. Han, J. Lee, and H. Shin, 'Si NanoCrystal Memory Cell with Room Temperature Single electron Effects,' Jpn. J. Appl. Phys., vol. 40, pp.447-451, 2001 https://doi.org/10.1143/JJAP.40.447
  11. Y. Shi, K. saito, H. Ishikuro, and T. Hiramoto, 'Effects of traps on charge storage characteristics in metal-oxidesemiconductor memory structures based on silicon annocrystal,' J. Appl. Phys., vol. 84, pp. 2358-2360, 1998 https://doi.org/10.1063/1.368346
  12. J. A. Wahl, H. Silva, A. Gokirnak, A. Kumar, J.J. Welser and S. Tiwari, 'Write, Erase and Storage Times ir; Nanocrystal Memories and the Role of Interface States,' in IEDM Tech. Dig., pp. 375-378, 1999 https://doi.org/10.1109/IEDM.1999.824173
  13. K. Han, I. Kim, and H. Shin, 'Programming Characteristics P-Channel Si Nano-Crystal Memory,' IEEE Electron Device Lett., vol. 21, pp. 313-315, 2000 https://doi.org/10.1109/55.843161
  14. K. Han, I. Kim, and H. Shin, 'Characteristics of P-channel Si Nano-Crystal Memory,' in IEDM Tech. Dig., pp. 309 -312, 2000 https://doi.org/10.1109/IEDM.2000.904318
  15. K. Han, I. Kim, and H. Shin, 'Characteristics of P-Channel Si Nano-Crsytal Memory,' IEEE Trans. Electron Devices, vo1.22, 2001. (to be published) https://doi.org/10.1109/16.918234
  16. Y. C. King, T. J. King, and C. Hu, 'MOS memory using germanium nanocrystals formed by thermal oxidation of $si-{1-x}\;Ge_x,' in IEDM Tech. Dig., pp. 115-118, 1998 https://doi.org/10.1109/IEDM.1998.746292
  17. Y. C. King, T. J. King, and C. Hu, 'A Long-Refresh Dynamic/Quasi-Nonvolatile Memory Device with 2-nm tunneling Oxide,' IEEE Electron Device Lett., vol. 20, pp. 409-411, 1999 https://doi.org/10.1109/55.778160
  18. H. C. Wann and C. Hu, 'High-Endurance Ultra-Thin Tunnel Oxide in MONOS Device Structure for Dynamic Memory Application,' IEEE Electron Device Lett., vol. 16, pp. 491-493,1995 https://doi.org/10.1109/55.468277
  19. K. Yano, T. Ishii, T. Hashimoto, T.Kobayashi, F.Murai, and K. Seki, 'Room temperature single electron memory,' IEEE Trans. Electron Devices, vol. 41, pp.1628-1638,1994 https://doi.org/10.1109/16.310117
  20. M. fukuda, K. Nakagawa, S. Miyazaki, and M. Hirose, 'Resonant tunneling through a self-assembled Si quantum dot,' Appl. Phys. Lett, vol. 70, pp. 2291-2293, 1997 https://doi.org/10.1063/1.118816