High Performance RF Passive Integration on a Si Smart Substrate for Wireless Applications

  • Received : 2002.07.11
  • Published : 2003.04.30


To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.



  1. IEDM Tech. Digest. Silicon as Microwave Substrate Reyes, A.C.
  2. Asia Pacific Microwave Conf. A New Millimeter-Wave IP-Chip on Silicon Substrate Sakai, H.
  3. IEDM Tech. Digest Monolithic Planar Inductor and Waveguide Substrate on Silicon with Performance Comparable to Those in GaAs MMIC Kim, B.K.;Ko, B.K.;Lee, K.
  4. IEEE Microwave Guided Wave Lett. v.7 no.8 High Performance Planar Inductor on Oxidized Porous Silicon (OPS) Substrate Nam, Choong-Mo;Kwon, Young-Se
  5. IEEE Electron Device Lett. v.22 no.6 Spiral inductors on Si p/p+ Substrate with Resonant Frequency of 20GHz Kim, Han-Su;Zheng, Dawei;Becker, A.J.;Xie, Ya-Hong
  6. 2002 Pan Pacific Microelectronics Symp. Ultra High Q Inductor and RF Integrated Passive Devices on Thick Oxide Si Substrate Kim, Dong-Wook;Jeong, In-Ho;Lee, Chang-Yup;Nam, Choong-Mo;Kong, Tong-Ook;Sung, Ho-Sung;Kim, Ki-Joong;Yoon, Il-Do;Lee, Jong-Soo;Kwon, Young-Se
  7. The 52nd Electronic Components and Technology Conf. High Quality RF Passive Integration on Silicon Using 35 um Thick Oxide Manufacturing Technology Jeong, In-Ho;Nam, Choong-Mo;Lee, Chang-Yup;Moon, Jung-Hoon;Lee, Jong-Soo;Kim, Dong-Wook;Kwon, Young-Se
  8. 2002 IEEE Int'l Microwave Symp. High Performance RF Passive Integration on Si Smart Substrate Kim, Dong-Wook;Jeong, In-Ho;Ho-Sung;Kong, Tong-Ook;Lee, Jong-Soo;Nam, Chonng-Mo;Kwon, Young-Se
  9. IEEE Electron Device Lett. v.12 no.1 Microwave Performance of SOI n-MOSFETs and Coplanar Waveguides Caviglia, A.L.;Potter, R.C.;West, L.J.
  10. IEEE Microwave and Guided Wave Lett. v.9 no.1 $SiO_2$Interface Layer Effects on Microwave Loss of High-Resistivity CPW Line Wu, Y.;Gamble, S.;Amstrong, B.M.;Fusco, V.F.;Stewart, J.A.C.
  11. IEEE Microwave and Guided Wave Lett. v.9 no.10 Low-Loss CPW Lines on Surface Stabilized High-Resistivity Silicon Gamble, H.S.;Amstrong, B.M.;Mitchell, S.J.N.;Wu, Y.;Fusco, V.F.;Stewart, J.A.C.