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Characterization of Pt/BLT/CeO2/Si Structures using CeO2 Buffer Layer

CeO2Buffer Layer를 이용한 Pt/BLT/CeO2/Si 구조의 특성

  • 이정미 (중앙대학교 전자전기공학부) ;
  • 김경태 (중앙대학교 전자전기공학부) ;
  • 김창일 (중앙대학교 전자전기공학부)
  • Published : 2003.10.01

Abstract

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

Keywords

MFIS;BLT;$CeO_2$;Memory window;MOD

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