- Volume 2 Issue 2
A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.
Phase Detector;Delay-Locked Loop
- T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa, 'A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500Mbps DRAM,' IEEE J. Solid-State Circuits, VoI.29, No. 12, pp. 1491-1496, Dec 1994 https://doi.org/10.1109/4.340422
- M. Steyaert, J. Janssens, B. Muer, M. Borremanc, N. Itoh, 'A 2V CMOS Cellular Transceiver Front-End,' in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 142-143
- Behzad Razavi, RF Microelectronics, Prentice Hall, 1997
- S.H. Wang, J. Gil, I. Kwon, H. Ahn, H. Shin, B. Kim, 'A 5-GHz Band I/Q Clock Generator using a Self Calibration Technique,' Proceedings ofthe 28th European Solid-State Circuit Conference, Sep. 2002, pp. 807 - 810
- Chan Hong Park, Beomsup Kim, 'A Low-Noise, 900-MHz VCO in 0.6-um CMOS,' IEEE J. SolidState Circuits, Vol. 34, No.5, pp. 586-591, May 1999 https://doi.org/10.1109/4.760367