Analysis of Power Noises by Chip-to-Chip Power Coupling on High-Speed Memory Modules

고속 메모리 모듈에서 칩 간의 파워커플링에 의한 파워 잠음 분석

  • 위재경 (숭실대학교 공과대학 정보통신공학부)
  • Published : 2004.10.01

Abstract

This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM and FBGA-based DIMH In controversy with common concepts, we find that the noise-isolation characteristics of FBGA package are more weak and sensitive on transferred noises than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.

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