A DLL-Based Frequency Synthesizer for Generation of Various Clocks

가변 클록 발생을 위한 DLL 주파수 합성기

  • 이지현 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 송윤귀 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 최영식 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 최혁환 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 류지구 (부경대학교 전자컴퓨터정보통신공학부)
  • Published : 2004.10.01


This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.


  1. K. Kurita, T. Hotta, and N. Kitamura, 'PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor', IEEE J. Solid State Circuits, vol. 26, pp. 585-589, APR. 1991 https://doi.org/10.1109/4.75059
  2. I. W. Young, J. K. Greason, and K. L. Wong, 'A PLL clock generator with 5 to 110MHz of lock range for microprocessors', IEEE J. Solid State Circuits, vol. 34, pp.1599-1607, NOV. 1992
  3. J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, 'A wide band width low voltage PLL for power PC microprocessors', IEEE J. Solid State Circuits, vol. 30, pp. 383-391, APR. 1995 https://doi.org/10.1109/4.375957
  4. V. R. von Kaenel, 'A high speed, low power clock generator for a microprocessor application... IEEE J. Solid State Circuits, vol. 33, pp. 1634-1639, NOV. 1998 https://doi.org/10.1109/4.726549
  5. George Chien, Paul R. Gray, 'A 900-MHz local oscillator using a DLL_based frequency multiplier technique for PCS applications', IEEE J. Solid State Circuits, vol. 35, pp. 1996-1999, DEC. 2000 https://doi.org/10.1109/4.890315
  6. David J. Foley, Michael P. Flynn, 'CMOS DLL_based 2V 3.2ps jitter 1GHz clock synthesizer and temperature compensated tunable oscillator', IEEE J. Solid State Circuits, vol. 36, pp. 417-423, MARCH 2001 https://doi.org/10.1109/4.910480
  7. Chul-woo Kim, In-Chul Hwang, and Sung-Mo Kang, 'A low power small area $\pm$ 7.23ps jitter 1GHz DLL_based clock generator', IEEE J. Solid State Circuits, vol. 37, pp. 1414-1420, NOV. 2002 https://doi.org/10.1109/JSSC.2002.803936
  8. Guang-Kaai Edhng, Jyh-Woei Lin, Shen-Iuan Liu, 'A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm', IEEE J. Solid State Circuits, vol. 36, pp. 1464-1471, OCT. 2001 https://doi.org/10.1109/4.953474