Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)
- Volume 8 Issue 6
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- Pages.1153-1157
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- 2004
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- 2234-4772(pISSN)
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- 2288-4165(eISSN)
Abstract
This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a
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