Design of RISC-based Transmission Wrapper Processor IP for TCP/IP Protocol Stack

TCP/IP프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서 IP 설계

  • 최병윤 (동의대학교 컴퓨터공학과) ;
  • 장종욱 (동의대학교 컴퓨터공학과)
  • Published : 2004.10.01


In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.


  1. L. Roberts, 'Internet Still Growing Dramatically Says Internet Founder' http://www., Aug, 2001
  2. Marc Necker, Didier Contis, and David Schimmel, 'TCP-Stream Reassembly and State Tracking in Hardware', Proc. of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM'02), pp.1-2, 2002
  3. W. Doeringer, and D. Dykeman, etc. 'A Survey of Light Weight Transport Protocols for High-Speed Networks,' IEEE Trans. on Communications, vol. 38, no.11, pp.2025-2039, Nov., 1990
  4. 진교홍, 고속 실시간 통신을 위한 TCP/IP 프로토콜의하드웨어 설계 및 구현, 부산대학교 컴퓨터 공학과 공학박사 논문 1997. 8
  5. David V. Schuehler, and John W. Lockwood, 'Tep Splitter: A TCPJIP Flow Monitor in Reconfigurable Hardware,' IEEE Micro pp.54-59, Jan.-Feb. 2003
  6. D. Clack and V. Jacobson, 'An Analysis of TCP Processing Overhead,' IEEE Communications Magazine, vol. 27, no.6, pp.23-29, June, 1989
  7. Axel Jantsch, 'Networks on Chip', ESD Laboratory, Royal Institute of Technology, Sweden, http://www.imit.kth.sejinfo/FOFU
  8. Florian Braun, John Lockwood, Marcel Waldvogel, 'Layered Protocol Wrapper for Internet Packet Processing in Reconfigurable Hardware,' Technical Report, WUC5-01-10, Department of Computer Science, Washington University, July, 2001
  9. Tsai Chi Huang, 'UDP/TCPlIP Packet Processing Using a Superscalar Microprocessor', Ph.D Thesis, Georgia Institute of Technology, December, 2000
  10. Paul Chow, The MIPS-X RISC Microprocessor, Kluwer Academic Publisher, 1989
  11. R. Braden, 'Computing the Internet Checksum', rfc1071, 1988