Design of RISC-based Transmission Wrapper Processor IP for TCP/IP Protocol Stack

TCP/IP프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서 IP 설계

  • 최병윤 (동의대학교 컴퓨터공학과) ;
  • 장종욱 (동의대학교 컴퓨터공학과)
  • Published : 2004.10.01

Abstract

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

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