- Volume 5 Issue 1
Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.