Performance Enhancement of CORDIC Employing Redundant Numbers and Minimal Iterations

잉여 수와 최소 반복 횟수를 이용한 CORDIC 성능 향상

  • 김승열 (충북대학교 정보통신공학과) ;
  • 유영갑 (충북대학교 전기전자컴퓨터공학부)
  • Published : 2006.02.01

Abstract

This paper presents a high performance CORDIC circuit based on redundant numbers yielding a minimal number of iteration stages. The minimal number of iteration stages reflects the iteration number yielding a smaller computation error than the truncation error. The minimal number of iterations is found n-4 for $n\geq16$, where n is the number of input angle bits. The CORDIC circuit is based on a redundant number system with a constant scale factor The circuit performs sine and cosine calculations with a delay of {5 (n-4)+ 2[$log_{2}n$]}$\DeltaT$.

Keywords

CORDIC;Redundant Numbers