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Optimal Scheduling of SAD Algorithm on VLIW-Based High Performance DSP

VLIW 기반 고성능 DSP에서의 SAD 알고리즘 최적화 스케줄링

  • 유희재 (숭실대학교 정보통신전자공학부) ;
  • 정수환 (숭실대학교 정보통신전자공학부) ;
  • 정선태 (숭실대학교 정보통신전자공학부)
  • Published : 2007.12.28

Abstract

SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

Keywords

SAD Algorithm;VLIW;DSP;Software Pipelining;Block Matching;Motion Picture Coding;SAD