Efficient Simulation Acceleration by FPGA Compilation Avoidance

FPGA 컴파일 회피에 의한 효과적인 시뮬레이션 가속

  • 심규호 (부산대학교 대학원 컴퓨터공학과) ;
  • 박창호 (동양시스템즈 IT서비스운영팀) ;
  • 양세양 (부산대학교 컴퓨터공학과)
  • Published : 2007.06.30


In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.


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