Verification of System using Master-Slave Structure

Master-Slave 기법을 적용한 System Operation의 동작 검증

  • 김인수 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부)
  • Published : 2009.01.01

Abstract

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

References

  1. Laung-Terng Wang, Charles E. Stroud and Nur A Touba, 'System On Chip Test Architectures Nanometer Thsign For Testability,' :Morgan Kaufmann Publishers, 2008
  2. Laung-Terng Wang, Cheng-Wen Wu and Xiaoqqing Wen, 'VLSI Test Principles and Architectures Design For Testability,' Morgan Kaufmann Publishers, 2006
  3. Bushnell, M.L. and Agrawal, V.D., 'Essentials of Electronic Testing,' Academic publishers, 2000
  4. Abramovici, M., Breuer, M.A and Friedman, D., 'Digital Systems Testing and Testable Design,' Computer Science Press, 1990
  5. Miczo, A, 'Digital Logic Testing and Simulation,' John Wiley & Sons, 1986
  6. Eichelberger,E.B. and Williams,T.W., 'A Logic Design Structure for LSI Testability,' Proc.14th Design Automation Conf. June, 1977
  7. Sedra Abramovici,M., Breuer,M.A and Friedman, A.D., 'Digital Systems Testing And Testable Design,' IEEE Press, 1990
  8. http://www.synopsys.com. 2008
  9. Michael D. Ciletti, 'Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL,' Prentice Hall, 1999
  10. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 'Digital Integrated Circuit-A Design Perspective 2nd Edition,' Prentice Hall, 2003
  11. Mark Bums and Gordon W. Roberts, 'An Introduction to Mixed-Signal IC Test and Measurement,' Oxford University Press, 2001