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Implementation of H.264/SVC Decoder System based on C-Model Simulator

C-모델 시뮬레이터 기반 H.264/SVC 복호기 시스템 구현

  • 정차근 (호서대학교 공과대학 시스템제어공학과) ;
  • 길대남 (호서대학교 공과대학 시스템제어공학과)
  • Published : 2009.02.28

Abstract

In this paper, we present result of embedded system based H.264/SVC decoder circuit design and system implementation. To deal with the standardized H.264/SVC functionalities, the presented SVC decoder system is consist of hardware engine design and software with ARM core processor. In order to improve the feasibility and applicability, and reduce the decoder complexity, the implemented system is constructed with only the consideration of IPPP structure scalability without using the full B-picture architecture. Finally, we will show the decoding image result using the designed H.264/SVC decoder system.

Keywords

H.264/SVC Decoder;C-model Simulator;Scalable Baseline Profile;Scalable;Hardware Engine;Embedded System

References

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