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Multiple Network-on-Chip Model for High Performance Neural Network

  • Dong, Yiping (The Graduate School of Information, Production and Systems, Waseda University) ;
  • Li, Ce (The Graduate School of Information, Production and Systems, Waseda University) ;
  • Lin, Zhen (The Graduate School of Information, Production and Systems, Waseda University) ;
  • Watanabe, Takahiro (The Graduate School of Information, Production and Systems, Waseda University)
  • Received : 2009.10.01
  • Published : 2010.03.31

Abstract

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

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