Design of an Asynchronous Instruction Cache based on a Mixed Delay Model

혼합 지연 모델에 기반한 비동기 명령어 캐시 설계

  • 전광배 (충북대학교 정보통신 공학과) ;
  • 김석만 (충북대학교 정보통신 공학과) ;
  • 이제훈 (강원대학교 전자공학과) ;
  • 오명훈 (한국전자통신연구원) ;
  • 조경록 (충북대학교 정보통신 공학과)
  • Received : 2010.01.26
  • Accepted : 2010.03.22
  • Published : 2010.03.28


Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.


Completion Signal;Cache Memory;Delay-Insensitive;CAM


Supported by : 교육과학기술부, 한국산업기술재단


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