Development of Simulator using RAM Disk for FTL Performance Analysis

RAM 디스크를 이용한 FTL 성능 분석 시뮬레이터 개발

  • Ihm, Dong-Hyuk (Dept. of Electronics and Computer Engineering, Chonnam National University) ;
  • Park, Seong-Mo (Dept. of Electronics and Computer Engineering, Chonnam National University)
  • 임동혁 (전남대학교 전자컴퓨터공학과) ;
  • 박성모 (전남대학교 전자컴퓨터공학과)
  • Received : 2010.06.03
  • Published : 2010.09.25


NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.



  1. AGRAWAL, N., PRABHAKARAN, V., WOBBER, T., DAVIS, J. D., MANASSE, M. S., AND PANIGRAHY, R. "Design tradeoffs for ssd performance." In Proceedings of the USENIX Annual Technical Conference, pp. 57-70, June 2008.
  2. E. GAL AND S. TOLEDO. "Algorithms and Data Structures for Flash Memories," ACM Computing Survey 37, 2, 138-163, June 2005
  3. W. G. Jeon and Y. S. Cho, "An equalization technique for OFDM and MC-CDMA in a multipath fading channels," in Proc. of IEEE Conf. on Acoustics, Speech and Signal Processing, pp. 2529-2532, Munich, Germany, May 1997.
  4. JUNG, D., CHAE, Y., JO, H., KIM, J., AND LEE, J. "A Group-based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems." In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 160-164. 17, September 2007.
  5. GANGER, G., WORTHINGTON, B., AND PATT, Y. "The DiskSim Simulation Environment Version 3.0 Reference Manual."
  6. GUPTA, A., KIM, Y., AND URGAONKAR, B. "DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page level AddressMappings". In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating System (ASPLOS), pp. 229-240, March 2009.
  7. KANG, J., JO, H., KIM, J., AND LEE, J. "A Superblock-based Flash Translation Layer for NAND Flash Memory." In Proceedings of the International Conference on Embedded Software (EMSOFT), pp. 161-170, October 2006.
  8. LEE, S., PARK, D., CHUNG, T., LEE, D., PARK, S., AND SONG, H. "A Log Buffer based Flash Translation Layer Using Fully Associative Sector Translation". IEEE Transactions on Embedded Computing Systems 6, 3, 18, 2007.