Design of 1/4-rate Clock and Date Recovery Circuit for High-speed Serial Display Interface

고속 직렬 디스플레이 인터페이스를 위한 1/4-rate 클록 데이터 복원회로 설계

  • 정기상 (전북대학교 전자정보공학부) ;
  • 김강직 (전북대학교 전자정보공학부) ;
  • 조성익 (전북대학교 전자공학부)
  • Received : 2010.12.31
  • Accepted : 2011.01.26
  • Published : 2011.02.01


4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.


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