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Design of 1/4-rate Clock and Date Recovery Circuit for High-speed Serial Display Interface

고속 직렬 디스플레이 인터페이스를 위한 1/4-rate 클록 데이터 복원회로 설계

  • 정기상 (전북대학교 전자정보공학부) ;
  • 김강직 (전북대학교 전자정보공학부) ;
  • 조성익 (전북대학교 전자공학부)
  • Received : 2010.12.31
  • Accepted : 2011.01.26
  • Published : 2011.02.01

Abstract

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

References

  1. T. Palkert, "A review of current standards activite s for high speed physical layers," Proc. 5th Internatio nal Workshop on System-on-Chip for Real-Time Ap plications, pp. 495-499, July 2005.
  2. Fuji Yang, Joseph Othmer, et al., "A CMOS low-power multiple 2.5-3.125Gb/s serial link macrocell for high IO bandwidth network ICs," IEEE J. of Solid-S tate Circuits, Vol.37, no. 12, Dec. 2002.
  3. Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. and Beomsup Kim "A Four-Channel 3.125-Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005
  4. Rainer Kreienkamp, Hubert Siedhoff, et al., "A 10-Gb/s CMOS clock and data recovery with an analog phase interpolator," IEEE J. of Solid-State Circuits, no. 3, Mar. 2005.
  5. VESA, "DisplayPort 1.1a Standard," Jan. 11, 2008.
  6. www.hdmi.org "HDMI Specification 1.3a"