Verification of New Family for Cascade Multilevel Inverters with Reduction of Components



Banaei, M.R.;Salary, E.

  • 투고 : 2010.05.19
  • 심사 : 2010.11.15
  • 발행 : 2011.03.01


This paper presents a new group for multilevel converter that operates as symmetric and asymmetric state. The proposed multilevel converter generates DC voltage levels similar to other topologies with less number of semiconductor switches. It results in the reduction of the number of switches, losses, installation area, and converter cost. To verify the voltage injection capabilities of the proposed inverter, the proposed topology is used in dynamic voltage restorer (DVR) to restore load voltage. The operation and performance of the proposed multilevel converters are verified by simulation using SIMULINK/MATLAB and experimental results.


Cascaded multilevel converter;New topology;Reduction of components;DVR


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