Verification of New Family for Cascade Multilevel Inverters with Reduction of Components

DOI QR코드

DOI QR Code

Banaei, M.R.;Salary, E.

  • 투고 : 2010.05.19
  • 심사 : 2010.11.15
  • 발행 : 2011.03.01

초록

This paper presents a new group for multilevel converter that operates as symmetric and asymmetric state. The proposed multilevel converter generates DC voltage levels similar to other topologies with less number of semiconductor switches. It results in the reduction of the number of switches, losses, installation area, and converter cost. To verify the voltage injection capabilities of the proposed inverter, the proposed topology is used in dynamic voltage restorer (DVR) to restore load voltage. The operation and performance of the proposed multilevel converters are verified by simulation using SIMULINK/MATLAB and experimental results.

키워드

Cascaded multilevel converter;New topology;Reduction of components;DVR

참고문헌

  1. Z. Pan, F.Z. Peng, “Harmonics optimization of the voltage balancing control for multilevel converter/ inverter systems”, IEEE Trans. Power Electronics, pp. 211-218, 2006. https://doi.org/10.1109/TPEL.2005.861158
  2. L.M. Tolbert, F. Z. Peng, T. Cunnyngham, J. N. Chiasson, “Charge Balance Control Schemes for Cascade Multilevel Converter in Hybrid Electric Vehicles,” IEEE Trans. Industrial Electronics, Vol. 49, No. 5, pp. 1058-1064, Oct. 2002. https://doi.org/10.1109/TIE.2002.803213
  3. S. Mariethoz, A. Rufer, “New configurations for the three-phase asymmetrical multilevel inverter,” in Proceeding of the IEEE 39th Annual Industry Applications Conference, pp. 828-835, Oct. 2004.
  4. J.Rodriguez, J.S. Lai, F.Z. Peng, “Multilevel Inverter: A Survey of Topologies, Controls, and applications”, IEEE Trans. on Industrial Electronics, Vol. 49, No. 4, August. 2002. https://doi.org/10.1109/TIE.2002.801052
  5. J.S. Lai, F.Z. Peng, “Multilevel Converters-A New Breed of power Converters”, IEEE Trans. Industry Application, Vol. 32, No. 3, pp. 509-517, MAY/JUNE. 1996. https://doi.org/10.1109/28.502161
  6. E. Babaei, S.H. Hosseini, “New cascaded multilevel inverter topology with minimum number of switches”, Energy Conversion and Management, Vol. 50, pp. 2761-2767, 2009. https://doi.org/10.1016/j.enconman.2009.06.032
  7. L.M. Tolbert , T.G. Habetler, “Novel Multilevel Inverter Carrier-Based PWM Method”, IEEE Trans. Industry Application, Vol. 35, No.5, pp. 1098-1107, September/October. 1999. https://doi.org/10.1109/28.793371
  8. D.W. Kang, Y.H. Lee, B.S. Suh,C.H. Choi, D.S. Hyun, “An Improved Carrier-Based SVPWM Method Using Leg Voltage Redundancies in Generalized Cascaded Multilevel Inverter Topology,” IEEE Trans. Power Electronics, Vol. 18, No. 1, pp. 180-187, January. 2003. https://doi.org/10.1109/TPEL.2002.807187
  9. K.A. Corzine, Y.L. Familiant, “A New Cascaded Multi-Level H-Bridge Drive,” IEEE Trans. on Power Electronics, Vol. 17, No. 1, pp.125-131, January. 2002. https://doi.org/10.1109/63.988678
  10. A. K. Jindal, A. Ghosh, A. Joshi, “Critical load bus voltage control using DVR under system frequency variation”, Electric Power Systems Research, pp. 255-263, 2008.
  11. M.R. Banaei, S.H. Hosseini, S. Khanmohamadi, G.B. Gharehpetian, “Verification of a new energy control strategy for dynamic voltage restorer by simulation”, Simulation Modeling Practice and Theory, 14 (2), pp.112-125, 2006. https://doi.org/10.1016/j.simpat.2005.03.001
  12. M.H. Haque, “Compensation of Distribution System Voltage Sag by DVR and D-STATCOM,” in Proceeding of PPT 2001.Conf. IEEE Porto Power Tech, Porto, Portugal. 2001.

피인용 문헌

  1. 1. Selection of DC voltage magnitude using Fibonacci series for new hybrid asymmetrical multilevel inverter with minimum PIV vol.53, pp.3, 2014, doi:10.5370/JEET.2011.6.2.245
  2. 2. Fault ride-through capability enhancement of DFIG-based wind turbine using novel dynamic voltage restorer based on two switches boost converter coupled with quinary multi-level inverter 2017, doi:10.5370/JEET.2011.6.2.245
  3. 3. New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count vol.27, pp.04, 2018, doi:10.5370/JEET.2011.6.2.245
  4. 4. Reduction of Components in Cascaded Transformer Multilevel Inverter Using Two DC Sources vol.7, pp.4, 2012, doi:10.5370/JEET.2011.6.2.245
  5. 5. Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters vol.7, pp.5, 2014, doi:10.5370/JEET.2011.6.2.245
  6. 6. Enhancement of DFIG-Wind Turbine’s LVRT capability using novel DVR based Odd-nary Cascaded Asymmetric Multi-Level Inverter vol.20, pp.3, 2017, doi:10.5370/JEET.2011.6.2.245
  7. 7. Optimal configuration for cascaded voltage source multilevel inverter based on series connection sub-multilevel inverter vol.3, pp.1, 2016, doi:10.5370/JEET.2011.6.2.245
  8. 8. An Innovative Scheme of Symmetric Multilevel Voltage Source Inverter With Lower Number of Circuit Devices vol.62, pp.11, 2015, doi:10.5370/JEET.2011.6.2.245