- Volume 12 Issue 1
A memory system with the linear skewing scheme has been regarded as one of suitable memory systems for a single instruction, multiple data (SIMD) architecture. The memory system supports simultaneous access n data to m memory modules within various access types with a constant interval in an arbitrary position in two dimensional data array of
Parallel Memory;Multiaccess Memory System;SIMD Architecture
- D. B. Kirk and Wen-mei W. Hwu, Programming Massively Parallel Processors: A Hands-on Approach, Morgan Kaufmann Pub., 2010.
- T. G. Mattson, B. A. Sanders, and B. L. Massingill, Patterns for Parallel Programming, Addison-wesley Pub., 2005.
- D. T. Harper III. "Block, Multistride Vector, and FFT Accesses in Parallel Memory System," IEEE Trans. Parallel and Distributed Systems, Vol.2, No.1, pp.43-51, 1991(1). https://doi.org/10.1109/71.80188
- R. Raghavan and J. P. Hayes, "On Randomlu Interleaved Memories," Proc. Supercomputing '90, pp.49-58, 1990.
- N. B. MacDonald, "An Overview of SIMD Parallel System: AMT DAP, Thinking Machines CM-200, and MasPar MP-1," Proc. Workshop Parallel Computing, 1992(4).
- K. Kim and V. K. P Kumar, "Perfect Latin Squares and Parallel Array Access," Pro. Int'l Symp. Computer Architecture, pp.372-379, 1989.
- D. T. Harper III. "A Multiacess Frame Buffer Architecture," IEEE Trans. Computers, Vol.43, pp.618-622, 1994(5). https://doi.org/10.1109/12.280810
- P. Budnik and D. J. Kuck, "The Organization and USe of Parallel Memories," IEEE Trans. Computers, Vol.20, No.12, pp.1566-1569, 1971(12). https://doi.org/10.1109/T-C.1971.223171
- D. H. Lawire, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, Vol.24, No.12, pp.1145-1155, 1975(12). https://doi.org/10.1109/T-C.1975.224157
- D. C. Van Voorhis and T.H.Morrin, "Memory System for Image Processing," IEEE Trans. Computers, Vol.27, No.2, pp.113-125, 1978(2). https://doi.org/10.1109/TC.1978.1675045
- D. H. Lawrie and C. R. Vora, "The Prime Memory System for Array Access," IEEE Trans. Computers, Vol.31, No.5, pp.435-442, 1982(5). https://doi.org/10.1109/TC.1982.1676020
- J. W. Park, "An Efficient Buffer Memory System for Subarray Access," IEEE Trans. Parallel and Distributed Systems, Vol.12, No.3, pp.316-335, 2001(3). https://doi.org/10.1109/71.914779
- Eero Aho, Jarno Vanne, and T. D. Hamalainen, "Parallel Memory Architecture for Arbitrary Stride Access," In Proc. of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and System, pp.65-70, 2006(4).
- J. K. Tanskanen and T. Pitkanen, "Parallel Memory Architecture for TTA Processor," Proc. of the 7th Int. Conf. on Embedded Computer Sys.: Architecture Modelling, and Simulation," pp.273-283, 2007.
- Dionysios Reisis and Nikolaos Vlassopoulos, "Conflict-free Parallel Memory Accessing Techniques for FFT Architecture," IEEE Trans. on Circuits and Systems, Vol.55, No.11, pp.3438-3447, 2008(12). https://doi.org/10.1109/TCSI.2008.924889
- J. W. Park, "Multiaccess Memory System for Attached SIMD Computer," IEEE Trans. Computers, Vol.53, No.3, pp.1-14, 2004(3). https://doi.org/10.1109/TC.2004.1255787
- H. Lee and J. W. Park, "Parallel Processing System for Multi-Access Memory System," Proc. World Multi-conference of Systematics, Cybernetics, and Informatics, pp.561-565, 2000.
- H. Lee, H. K. Cho, D. S. You, and J. W. Park, "MAMS-PP4: Multi-Access Memory System used to improve the processing speed of Visual Media Applications in a Parallel Processing System," IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, Vol.E87-A, No.11, pp.2852-2858, 2004(11).