A Performance Study of Multi-core Out-of-Order Superscalar Processor Architecture

멀티코어 비순차 수퍼스칼라 프로세서의 성능 연구

  • 이종복 (한성대 공대 정보통신공학과)
  • Received : 2012.08.05
  • Accepted : 2012.09.20
  • Published : 2012.10.01


In order to overcome the hardware complexity and power consumption problems, recently the multi-core architecture has been prevalent. For hardware simplicity, usually RISC processor is adopted as the unit core processor. However, if the performance of unit core processor is enhanced, the overall performance of the multi-core processor architecture can be further increased. In this paper, out-of-order superscalar processor is utilized for the multi-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the out-of-order superscalar cores between 2 and 16 extensively. As a result, the 16-core out-of-order superscalar processor for the window size of 16 resulted in 17.4 times speed up over the single-core out-of-order superscalar processor, and 50 times speed up over the single core RISC processor. When compared for the same number of cores on the average, the multi-core out-of-order superscalar processor performance achieved 3.2 times speed up over the multi-core RISC processor and 1.6 times speed up over the multi-core in-order superscalar processor.


Multi-core processor;Superscalar processor;Out-of-order execution


Supported by : 한성대학교


  1. P. K. Dubey, G. B. Adams III, and M. J. Flynn, "Instruction Window Size Trade-Offs and Characterization of Program Parallelism," IEEE Transactions on Computers, vol. 43, pp 431-442, Apr. 1994.
  2. David E. Culler and Jaswinder Pal Singh, "Parallel Computer Architecture", Morgan Kauffmann Publishers, Inc. Aug. 1998.
  3. Stephen W. Keckler, Kunle Olukotun, and H. Peter Hofsee, "Multicore Processors and Systems", Springer. 2009.
  4. Theo Ungerer, Borut Robic, and Jurij Silk, "Multithreaded Processors", The Computer Journal, Vol. 45, No. 3, 2002
  5. D. Pham et. al, "The Design and Implementation of a First-Generation CELL processor", ISSCC 2005.
  6. Davy Genbrugge and Lieven Eeckhout, "Chip Multiprocessor Design Space Exploration through Statistical Simulation", IEEE Transactions on Computers 58(12), pp.1668-1681, Dec. 2009.
  7. Alejandro Rico, Alejandro Duran. Felipe Cabarcas, Yoav Etsion, Alex Ramirex, and Mateo Valero, "Trace-driven Simulation of Multithreaded Applications", ISPASS, 2011.
  8. T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
  9. T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, May. 1992, pp.124-134.