High-Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

  • Ryu, Namsik (Advanced Communications Research Laboratory, ETRI) ;
  • Jung, Jae-Ho (Advanced Communications Research Laboratory, ETRI) ;
  • Jeong, Yongchae (Division of Electronic Engineering, Chonbuk National University)
  • Received : 2012.03.30
  • Accepted : 2012.09.04
  • Published : 2012.12.31


This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.


Grant : Research on the Class-S base-station power amplifier technology for future mobile communications

Supported by : KEIT


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