Simulation and Fabrication Studies of Semi-superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

  • Na, Kyoung Il (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kim, Sang Gi (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Koo, Jin Gun (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kim, Jong Dae (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Yang, Yil Suk (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Lee, Jin Ho (Convergence Components & Materials Research Laboratory, ETRI)
  • Received : 2012.03.21
  • Accepted : 2012.07.19
  • Published : 2012.12.31


In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.


Grant : Development of High Voltage/Current Power Module and ESD for BLDC Motor

Supported by : KEIT


  1. P. Goarin et al., "Split-Gate Resurf Stepped Oxide (RSO) MOSFETs for 25V Applications with Record Low Gate-to-Drain Charge," Proc. ISPSD, 2007, pp. 61-64.
  2. G.E.J. Koops et al., "Resurf Stepped Oxide (RSO) MOSFET for 85V Having a Record Low Specific On-Resistance," Proc. ISPSD, 2004, pp. 185-188.
  3. Y. Wang et al., "Gate Enhanced Power UMOSFET with Ultralow On-Resistance," IEEE Electron Device Lett., vol. 31, no. 4, Apr. 2010, pp. 338-340.
  4. P. Moens et al., "XtreMOS: The First Integrated Power Transistor Breaking the Silicon Limit," Proc. IEDM. 2006, pp.1-4.
  5. Y.H. Lho and Y.S. Yang, "Design of 100-V Super-Junction Trench Power MOSFET with Low On-Resistance," ETRI J., vol. 34, no. 1, Feb. 2012, pp. 134-137.
  6. W. Saito et al., "High Breakdown Voltage (>1000 V) Semi-Superjunction MOSFETs Using 600-V Class Superjunction MOSFET Process," IEEE Trans. Electron Devices, vol. 52, no. 10, Oct. 2005, pp. 2317-2322.
  7. Y. Miura, H. Ninomiya, and K. Kobayashi, "High Performance Superjunction UMOSFETs with Split P-Columns Fabricated by Multi-Ion-Implantations," Proc. ISPSD, 2005, pp. 39-42.
  8. S. Yamauchi et al., "Fabrication of High Aspect Ratio Doping Region by Using Trench Filling of Epitaxial Si Growth," Proc. ISPSD, 2001, pp. 363-366.
  9. T. Minato et al., "Which Is Cooler, Trench or Muiti-Epitaxy? Cutting-Edge Approach for the Silicon Limit by the Super Trench Power MOS-FET (STM)," Proc. ISPSD, 2000, pp. 73-76.
  10. E. Napoli, H. Wang, and F. Udrea, "The Effect of Charge Imbalance on Superjunction Power Devices: An Exact Analytical Solution," IEEE Electron Device Lett., vol. 29, no. 3, Mar. 2008, pp. 249-251.
  11. C.W. Liu, S. Maikap and C.Y. Yu, "Mobility-Enhancement Technologies," IEEE Circuits Devices Mag., vol. 21, no. 3, May 2005, pp. 21-36.
  12. M.A. Gajda et al., "Industrialisation of Resurf Stepped Oxide Technology for Power Transistors," Proc. ISPSD, 2006, pp. 1-4.