A Performance Study on Many-core Processor Architectures with SPEC Benchmark Programs

SPEC 벤치마크 프로그램에 대한 매니코어 프로세서의 성능 연구

  • Lee, Jongbok (Dept. of Information and Communication Engineering, Hansung University)
  • 이종복 (한성대 정보통신공학과)
  • Received : 2012.12.15
  • Accepted : 2013.01.25
  • Published : 2013.02.01


In order to overcome the complexity and performance limit problems of superscalar processors, the multi-core architecture has been prevalent recently. Usually, the number of cores mostly used for the multi-core processor architecture ranges from 2 to 16. However in the near future, more than 32-cores are likely to be utilized, which is called as many-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the 32 to 1024 many-core architectures extensively. For 1024-cores, the average performance scores 15.7 IPC, but the performance increase rate is saturated.


Supported by : 한성대학교


  1. P. K. Dubey, G. B. Adams III, and M. J. Flynn, "Instruction Window Size Trade-Offs and Characterization of Program Parallelism," IEEE Transactions on Computers, vol. 43, pp 431-442, Apr. 1994.
  2. D. E. Culler and J. P. Singh, "Parallel Computer Architecture," Morgan Kauffmann Publishers, Inc. Aug. 1998.
  3. S. W. Keckler, K. Olukotun, and H. P. Hofsee, "Multicore Processors and Systems," Springer. 2009.
  4. T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
  5. D. Pham et. al, "The Design and Implementation of a First-Generation CELL processor," ISSCC 2005.
  6. D. Genbrugge and L. Eeckhout, "Chip Multiprocessor Design Space Exploration through Statistical Simulation," IEEE Transactions on Computers 58(12), pp.1668-1681, Dec. 2009.
  7. A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-driven Simulation of Multithreaded Applications," ISPASS, 2011.
  8. M. Frankilin, G. S. Sohi, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References," IEEE Transactions on Computers, Vol. 45, No. 5, May 1996.
  9. T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
  10. T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May 1992.
  11. S. Biswas, et. al, "Multi-Execution : Multicore Caching for Data-Similar Executions," International Symposium on Computer Architecture, Jun. 2009.
  12. M. Monchiero, et. al, "How to Simulate 1000 Cores," ACM SIGARCH Computer Architecture News archive, Vol. 37, Issue 2, May 2009, pp. 10-19
  13. A. Ghosh, S. Devadas, K. Keutzer and J. White, "Estimation of Average Switching Activity in Combinational and Sequential Circuits," ACM/IEE Design Automation Conf., pp. 253-259, 1992.

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