Implementation of sin/cos Processor for Descriptor on SIFT

SIFT의 descriptor를 위한 sin/cos 프로세서의 구현

  • Received : 2013.03.13
  • Accepted : 2013.04.02
  • Published : 2013.04.28


The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.


SIFT;Descriptor;sin/cos processor;FPGA


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