Easily Adaptable On-Chip Debug Architecture for Multicore Processors

  • Xu, Jing-Zhe (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Park, Hyeongbae (Department of R&D HW3 Team, Chips & Media Inc.) ;
  • Jung, Seungpyo (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Park, Ju Sung (Department of Electronics and Electrical Engineering, Pusan National University)
  • Received : 2012.07.18
  • Accepted : 2012.10.01
  • Published : 2013.04.01


Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.


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