3차원 실장을 위한 TSV의 Cu 전해도금 및 로우알파 솔더 범핑

DOI QR코드

DOI QR Code

정도현;쿠마르산토쉬;정재필
Jung, Do hyun;Kumar, Santosh;Jung, Jae pil

  • 투고 : 2015.12.01
  • 심사 : 2015.12.22
  • 발행 : 2015.12.30

초록

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

키워드

three dimensional packaging;TSV (Through Silicon Via);Cu filling;low alpha;solder bumping

참고문헌

  1. J. H. Jun, I. R. Kim, M. Mayer, Y. N. Zhou, S. B. Jung, and J. P. Jung, "A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging", Materials Transactions, 51(10), 1887 (2010). https://doi.org/10.2320/matertrans.M2009314
  2. S. Kumar, D. H. Jung, and J. P. Jung, "High-Speed Shear Test for Low Alpha Sn-1.0%Ag-0.5%Cu (SAC-105) Solder Ball of Sub-100-${\mu}m$ Dimension for Wafer Level Packaging", IEEE Trans. Compon., Packag, Manuf. Technol., 3(3), 441 (2013). https://doi.org/10.1109/TCPMT.2012.2230688
  3. S. J. Hong, Y. W. Lee, K. S. Kim, K. J. Lee, J. O. Kim, J. H. Park, and J. P. Jung, "Filling via hole in Si-wafer for 3 Dimensional Packaging", Proc. The Korean Welding and Joining Society (KWS), Samcheok, 227 (2006).
  4. W. Seo, J. H. Park, J. Y. Lee, M. K. Cho, and G. S. Kim, "Via Cleaning Process for Laser TSV Process", J. Microelectron. Packag. Soc., 16(1), 45 (2009).
  5. S. P. Shen, W. H. Chen, W. P. Dow, T. Kamitamari, E. Cheng, J. Y. Lin, and W. C. Chang, "Copper seed layer repair using an electroplating process for through silicon via metallization", Microelectronic Engineering, 105, 25 (2013). https://doi.org/10.1016/j.mee.2012.12.017
  6. T. Kenji, T. Hiroshi, T. Yoshihiro, Y. Yasuhiro, H. Masataka, S. Tomotoshi, M. Tadahiro, and B. Manabu, "Current status of research and development for three-dimensional chip stack technology", J. Appl. Phys., 40, 3032 (2001). https://doi.org/10.1143/JJAP.40.3032
  7. R. Lee, R. Hon, and C. K. Wong, "3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling", Proc. 55th Elec. Pack. Tech. Conf. (EPTC), Lake Buena Vista, 795 (2005).
  8. H. Lee, M. Choi, S. H. Kwon, J. H. Lee, and Y. Kim, "Characteristic of Through Silicon Via's Seed Layer Deposition and Via Filling". Kor. J. Mater. Res, 23(10), 550 (2013). https://doi.org/10.3740/MRSK.2013.23.10.550
  9. B. H. Kim, H. C. Kim, K. J. Chun, J. H. Ki, and Y. S. Tak, "Cantilevert-type microelectromechanical systems probe card with through-wafer interconnects for fine pitch and highspeed testing", J. Applied Physics, 43(6B), 3877 (2004). https://doi.org/10.1143/JJAP.43.3877
  10. F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y. Civale, P. Leunissen, M. Kondo, E. Webb, and S. Shingubara, "Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias", Electrochimica Acta, 100(30), 203 (2013). https://doi.org/10.1016/j.electacta.2013.03.106
  11. M. Knaut, M. Junige, V. Neumann, H. Wojcik, T. Henke, C. Hossbach, A. Hiess, M. Albert, and J. W. Bartha, "Atomic layer deposition for high aspect ratio through silicon vias", Microelec. Eng., 107, 80 (2013). https://doi.org/10.1016/j.mee.2013.01.031
  12. S. Yamamoto, K. Itoi, T. Suemasu, and T. Takizawa, "Si through-hole interconnections filled with Au-Sn solder by molten metal suction method", Proc. 16th IEEE International Conference, Kyoto, 642 (2003).
  13. C. Lee, S. Tsuru, Y. Kanda, S. Ikeda, and M. Matsumura, "Formation of 100-${\mu}m$-deep Vertical Pores in Si Wafers by Wet Etching and Cu Electrodeposition", J. Electrochem. Soc., 156(12), D543 (2009). https://doi.org/10.1149/1.3237139
  14. T. Hayashi, K. Kondo, T. Saito, M. Takeuchi, and N. Okamoto, "High-Speed Through Silicon Via(TSV) Filling Using Diallylamine Additive", J. Electrochem. Soc., 158(12), 715 (2011).
  15. H. Y. Li, E. Liao, X. F. Pang, H. Yu, X. X. Yu, and J. Y. Sun, "Fast Electroplating TSV Process Development for the Via-Last Approach", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 777, IEEE Components (2010).
  16. H. Banha, A. Funabashi, and F. Kondo, "High speed TSV filling", Proc. 24th Micro Electron. Sympo. (MES), Osaka, 53 (2015).
  17. A. Pohjoranta and R. Tenno, "A Method for Microvia-Fill Process Modeling in a Cu Plating System with Additives", J. Electrochem. Soc., 154(10), D502 (2007). https://doi.org/10.1149/1.2761638
  18. I. R. Kim, S. C. Hong, and J. P. Jung, "High Speed Cu Filling into Tapered TSV for 3-dimensional Si Chip Stacking", J. Met. Mater., 49(5), 388 (2010).
  19. I. R. Kim, J. K. Park, Y. C. Chu, and J. P. Jung, "High speed Cu Filling Into TSV by Pulse Current for 3 Dimensional Chip Stacking", J. Met. Mater., 48(7), 667 (2010).
  20. S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung, "Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microelectronics Reliability, 51, 2228 (2011). https://doi.org/10.1016/j.microrel.2011.06.031
  21. S. C. Hong, D. H. Jung, J. P. Jung, and W. J. Kim, "Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking", Korean J. Met. Mater., 50(2), 152 (2012). https://doi.org/10.3365/KJMM.2012.50.2.152
  22. S. J. Lee, Y. J. Jang, J. H. Lee, and J. P. Jung, "Cu-Filling Behavior in TSV with Positions in Wafer Level", J. Microelectron. Packag. Soc., 21(4), 91 (2014).
  23. P. Dixit, C. W. Tan, L. Xu, N. Lin, J. Miao, J. Pang, P. Backus, and R. Preisser, "Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating", J. Miceomech. Microeng., 17(5), 1078 (2007). https://doi.org/10.1088/0960-1317/17/5/030
  24. S. J. Hong, J. H. Jun, J. P. Jung, and M. Mayer, "Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging", IEEE Transactions on Advanced Packaging, 33(4), 912 (2010). https://doi.org/10.1109/TADVP.2010.2049019
  25. S. Kumar, D. H. Jung, and J. P. Jung, "Wetting behavior and elastic properties of low alpha SAC105 and pure Sn solder", J. Mater. Sci.: Mater. Electron., 24(6), 1748 (2012).
  26. J. F. Ziegler and W. A. Lanford, "The effect of sea level cosmic rays on electronic devices", J. Appl. Phys., 52(6), 4305 (1981). https://doi.org/10.1063/1.329243
  27. D. H. Jung, A. Sharma, K. H. Kim, Y. C. Choo, and J. P. Jung, "Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping", J. Mater. Eng. and Perf., 24(3), 1107 (2015). https://doi.org/10.1007/s11665-015-1394-4

피인용 문헌

  1. 1. Fabrication and shear strength analysis of Sn-3.5Ag/Cu-filled TSV for 3D microelectronic packaging vol.12, pp.6, 2016, doi:10.6117/kmeps.2015.22.4.007

과제정보

연구 과제 주관 기관 : 서울시립대학교