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Multi-Size Circular Shifter Based on Benes Network with High-Speed 3×3 Switch

고속 3×3 스위치를 이용한 Benes 네트워크 기반 Multi-Size Circular Shifter

Kang, Hyeong-Ju
강형주

  • Received : 2015.09.01
  • Accepted : 2015.10.19
  • Published : 2015.11.30

Abstract

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

Keywords

cyclic-shifter;multi-size circular shifter;LDPC decoder;QC-LDPC decoder

References

  1. R. G. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: M.I.T. Press, 1963.
  2. D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, no. 18, pp.1645-1646, Aug. 1996. https://doi.org/10.1049/el:19961141
  3. R. M. Tanner, D. Sridhara, A. Sridharan, T. E. Fuja, and D. J. Costello, Jr., "LDPC block and convolutional codes based on circulant matrics," IEEE Transactions on Information Theory, vol. 50, no. 12, pp. 2966-2984, Dec. 2004. https://doi.org/10.1109/TIT.2004.838370
  4. M. Rovini, G. Gentile, and L. Fanucci, "Multi-size circular shifting networks for decoders of structured LDPC codes," Electronics Letters, vol. 43, no. 17, pp. 938-940, Aug. 2007. https://doi.org/10.1049/el:20071157
  5. X. Chen, S. Lin, and V. Akella, "QSN-A simple circularshift network for reconfigurable quasi-cyclic LDPC decoders," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 57, no. 10, pp. 782-786, Oct. 2010. https://doi.org/10.1109/TCSII.2010.2067811
  6. B. Xiang, D. Bao, S. Huang, and X. Zeng, "An 847-955 Mb/s 342-397 mW dual-path fully-overlapped QC-LDPC decoder for WiMAX system in $0.13{\mu}m$ CMOS," IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1416-1432, Jun. 2011. https://doi.org/10.1109/JSSC.2011.2125030
  7. D. Oh and K. K. Parhi, "Area efficient controller design of barrel shifters for reconfigurable LDPC decoders," in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 240-243, 2008.
  8. D. Oh and K. K. Parhi, "Low-complexity switch network for reconfigurable LDPC decoders," IEEE Transactions on Very Large Scale Integration(VLSI) Systems , vol. 18, no. 1, pp. 85-94, Jan. 2010. https://doi.org/10.1109/TVLSI.2008.2007736
  9. V. E. Benes, "Optimal rearrangeable multistage connecting networks," Bell System Technical Journal , vol. 43, no. 4, pp. 16410-1656, Jul. 1964.

Cited by

  1. Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes vol.39, pp.3, 2017, https://doi.org/10.4218/etrij.17.0116.0341
  2. Low-complexity, high-speed multi-size cyclic-shifter for quasi-cyclic LDPC decoder vol.54, pp.7, 2018, https://doi.org/10.1049/el.2017.4456