LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

  • Yu, Seog Kun (School of Electronics Engineering, Kyungpook National University) ;
  • Joo, Eon Kyeong (School of Electronics Engineering, Kyungpook National University)
  • Received : 2014.01.23
  • Accepted : 2014.11.04
  • Published : 2015.02.01


The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.


Supported by : Kyungpook National University


  1. R. Garello et al., "On Error Floor and Free Distance of Turbo Codes," IEEE Int. Conf. Commun., Helsinki, Finland, vol. 1, June 11-14, 2001, pp. 45-49.
  2. R.G. Gallager, "Low-Density Parity-Check Code," IRE Trans. Inf. Theory, vol. 8, no. 1, Jan. 1962, pp. 21-28.
  3. D.J.C. MacKay and R.M. Neal, "Near Shannon Limit Performance of Low-Density Parity-Check Codes," Electron. Lett., vol. 33, no. 6, Mar. 1997, pp. 457-458.
  4. S.H. Lee, J.A. Seok, and E.K. Joo, "Serial Concatenation of LDPC and Turbo Code for the Next Generation Mobile Communications," Wireless Opt. Commun. Netw., Dubai, UAE, Mar. 6-8, 2005, pp. 425-427.
  5. T. Richardson, "Error Floors of LDPC Codes," Annu. Conf. Commun. Contr. Comput., Monticello, IL, USA, Sept. 2003, pp. 1426-1435.
  6. X.-Y. Hu, E. Eleftheriou, and D.M. Arnold, "Regular and Irregular Progressive Edge-Growth Tanner Graphs," IEEE Trans. Inf. Theory, vol. 51, no. 1, Jan. 2005, pp. 386-398.
  7. ETSI EN 302 755 v1.1.1, Digital Video Broadcasting (DVB); Frame Sturcture Channel Coding and Modulation for a Second Generation Digital Terrestrial Television Broadcasting System (DVB-T2), Sept. 2009.
  8. E. Cavus and B. Daneshrad, "A Performance Improvement and Error Floor Avoidance Technique for Belief Propagation Decoding of LDPC Codes," Pers. Indoor Mobile Radio Commun., Berlin, Germany, vol. 4, Sept. 11-14, 2005, pp. 2386-2390.
  9. S.-K. Yu, S.-G. Kang, and E.-K. Joo, "A Modified Sum-Product Algorithm for Error-Floor Reduction in LDPC Codes," J. KICS, vol. 35, no. 5. May 2010, pp. 423-431.
  10. S.H. Lee et al., "Bit Probability Transition Characteristics of LDPC Code," IEEE Int. Conf. Telecommun., Tahiti, French Polynesia, vol. 1, Feb. 23-Mar. 1, 2003, pp. 553-557.
  11. S. Landner and O. Milenkovic, "Algorithmic and Combinatorial Analysis of Trapping Sets in Structured LDPC Codes," Wireless Netw., Commun. Mobile Comput., Maui, HI, USA, vol. 1, June 2005, pp. 630-635.
  12. Y. Han and W.E. Ryan, "Low-Floor Decoders for LDPC Codes," IEEE Trans. Commun., vol. 57, no. 6, June 2009, pp. 1663-1673.