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A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 ㎛ BCD

  • Kim, Hongjin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Park, Young-Jun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Park, Ju-Hyun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Ryu, Ho-Cheol (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Pu, Young-Gun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Minjae (School of Information and Communications, Gwangju Institute of Science and Technology (GIST)) ;
  • Hwang, Keumcheol (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Yang, Younggoo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2016.01.24
  • Accepted : 2016.07.10
  • Published : 2016.11.20

Abstract

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

Acknowledgement

Supported by : Information & communications Technology Promotion(IITP)

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